# SAM3U ADC12B

## Analog-to-Digital-Converter 12bits (ADC12B) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x400A8000 | Control Register | ADC12B_CR | write-only | -
0x400A8004 | Mode Register | ADC12B_MR | read-write | 0x00000000
0x400A8010 | Channel Enable Register | ADC12B_CHER | write-only | -
0x400A8014 | Channel Disable Register | ADC12B_CHDR | write-only | -
0x400A8018 | Channel Status Register | ADC12B_CHSR | read-only | 0x00000000
0x400A801C | Status Register | ADC12B_SR | read-only | 0x000C0000
0x400A8020 | Last Converted Data Register | ADC12B_LCDR | read-only | 0x00000000
0x400A8024 | Interrupt Enable Register | ADC12B_IER | write-only | -
0x400A8028 | Interrupt Disable Register | ADC12B_IDR | write-only | -
0x400A802C | Interrupt Mask Register | ADC12B_IMR | read-only | 0x00000000
0x400A8030 | Channel Data Register | ADC12B_CDR[8] | read-only | 0x0
0x400A8064 | Analog Control Register | ADC12B_ACR | read-write | 0x00000000
0x400A8068 | Extended Mode Register | ADC12B_EMR | read-write | 0x00000000
0x400A8100 | Receive Pointer Register | ADC12B_RPR | read-write | 0x00000000
0x400A8104 | Receive Counter Register | ADC12B_RCR | read-write | 0x00000000
0x400A8110 | Receive Next Pointer Register | ADC12B_RNPR | read-write | 0x00000000
0x400A8114 | Receive Next Counter Register | ADC12B_RNCR | read-write | 0x00000000
0x400A8120 | Transfer Control Register | ADC12B_PTCR | write-only | 0x00000000
0x400A8124 | Transfer Status Register | ADC12B_PTSR | read-only | 0x00000000

### Register Fields

#### ADC12B Control Register

Name: ADC12B_CR

Access: write-only

Address: 0x400A8000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | START | SWRST

- SWRST: Software Reset

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets the ADC12B simulating a hardware reset.

- START: Start Conversion

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Begins analog-to-digital conversion.

#### ADC12B Mode Register

Name: ADC12B_MR

Access: read-write

Address: 0x400A8004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | SHTIM
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
STARTUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PRESCAL
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | SLEEP | LOWRES | TRGSEL | TRGEN

- TRGEN: Trigger Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Hardware triggers are disabled. Starting a conversion is only possible by software.
  1 | - | Hardware trigger selected by TRGSEL field is enabled.

- TRGSEL: Trigger Selection

  Value | Name | Description
  --- | --- | ---
  0x0 | - | External trigger
  0x1 | - | TIO Output of the Timer Counter Channel 0
  0x2 | - | TIO Output of the Timer Counter Channel 1
  0x3 | - | TIO Output of the Timer Counter Channel 2
  0x4 | - | PWM Event Line 0
  0x5 | - | PWM Event Line 1

- LOWRES: Resolution

  Value | Name | Description
  --- | --- | ---
  0 | - | 12-bit resolution
  1 | - | 10-bit resolution

- SLEEP: Sleep Mode

  Value | Name | Description
  --- | --- | ---
  0 | - | Normal Mode
  1 | - | Sleep Modes (see OFFMODES register)

- PRESCAL: Prescaler Rate Selection

-

- STARTUP: Start Up Time

-

- SHTIM: Sample & Hold Time

-

#### ADC12B Channel Enable Register

Name: ADC12B_CHER

Access: write-only

Address: 0x400A8010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH7 | CH6 | CH5 | CH4 | CH3 | CH2 | CH1 | CH0

- CH0: Channel 0 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH1: Channel 1 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH2: Channel 2 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH3: Channel 3 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH4: Channel 4 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH5: Channel 5 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH6: Channel 6 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

- CH7: Channel 7 Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding channel.

#### ADC12B Channel Disable Register

Name: ADC12B_CHDR

Access: write-only

Address: 0x400A8014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH7 | CH6 | CH5 | CH4 | CH3 | CH2 | CH1 | CH0

- CH0

-

- CH1

-

- CH2

-

- CH3

-

- CH4

-

- CH5

-

- CH6

-

- CH7

-

#### ADC12B Channel Status Register

Name: ADC12B_CHSR

Access: read-only

Address: 0x400A8018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH7 | CH6 | CH5 | CH4 | CH3 | CH2 | CH1 | CH0

- CH0: Channel 0 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH1: Channel 1 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH2: Channel 2 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH3: Channel 3 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH4: Channel 4 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH5: Channel 5 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH6: Channel 6 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

- CH7: Channel 7 Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding channel is disabled.
  1 | - | Corresponding channel is enabled.

#### ADC12B Status Register

Name: ADC12B_SR

Access: read-only

Address: 0x400A801C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
OVRE7 | OVRE6 | OVRE5 | OVRE4 | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion 0

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC1: End of Conversion 1

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC2: End of Conversion 2

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC3: End of Conversion 3

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC4: End of Conversion 4

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC5: End of Conversion 5

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC6: End of Conversion 6

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- EOC7: End of Conversion 7

  Value | Name | Description
  --- | --- | ---
  0 | - | Corresponding analog channel is disabled, or the conversion is not finished.
  1 | - | Corresponding analog channel is enabled and conversion is complete.

- OVRE0: Overrun Error 0

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE1: Overrun Error 1

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE2: Overrun Error 2

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE3: Overrun Error 3

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE4: Overrun Error 4

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE5: Overrun Error 5

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE6: Overrun Error 6

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- OVRE7: Overrun Error 7

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error on the corresponding channel since the last read of ADC12B_SR.
  1 | - | There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.

- DRDY: Data Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | No data has been converted since the last read of ADC12B_LCDR.
  1 | - | At least one data has been converted and is available in ADC12B_LCDR.

- GOVRE: General Overrun Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No General Overrun Error occurred since the last read of ADC12B_SR.
  1 | - | At least one General Overrun Error has occurred since the last read of ADC12B_SR.

- ENDRX: End of RX Buffer

  Value | Name | Description
  --- | --- | ---
  0 | - | The Receive Counter Register has not reached 0 since the last write in ADC12B_RCR or ADC12B_RNCR.
  1 | - | The Receive Counter Register has reached 0 since the last write in ADC12B_RCR or ADC12B_RNCR.

- RXBUFF: RX Buffer Full

  Value | Name | Description
  --- | --- | ---
  0 | - | ADC12B_RCR or ADC12B_RNCR have a value other than 0.
  1 | - | Both ADC12B_RCR and ADC12B_RNCR have a value of 0.

#### ADC12B Last Converted Data Register

Name: ADC12B_LCDR

Access: read-only

Address: 0x400A8020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | LDATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LDATA

- LDATA: Last Data Converted

-

#### ADC12B Interrupt Enable Register

Name: ADC12B_IER

Access: write-only

Address: 0x400A8024

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
OVRE7 | OVRE6 | OVRE5 | OVRE4 | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion Interrupt Enable 0

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC1: End of Conversion Interrupt Enable 1

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC2: End of Conversion Interrupt Enable 2

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC3: End of Conversion Interrupt Enable 3

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC4: End of Conversion Interrupt Enable 4

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC5: End of Conversion Interrupt Enable 5

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC6: End of Conversion Interrupt Enable 6

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- EOC7: End of Conversion Interrupt Enable 7

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE0: Overrun Error Interrupt Enable 0

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE1: Overrun Error Interrupt Enable 1

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE2: Overrun Error Interrupt Enable 2

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE3: Overrun Error Interrupt Enable 3

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE4: Overrun Error Interrupt Enable 4

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE5: Overrun Error Interrupt Enable 5

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE6: Overrun Error Interrupt Enable 6

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE7: Overrun Error Interrupt Enable 7

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- DRDY: Data Ready Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- GOVRE: General Overrun Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ENDRX: End of Receive Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RXBUFF: Receive Buffer Full Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

#### ADC12B Interrupt Disable Register

Name: ADC12B_IDR

Access: write-only

Address: 0x400A8028

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
OVRE7 | OVRE6 | OVRE5 | OVRE4 | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion Interrupt Disable 0

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC1: End of Conversion Interrupt Disable 1

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC2: End of Conversion Interrupt Disable 2

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC3: End of Conversion Interrupt Disable 3

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC4: End of Conversion Interrupt Disable 4

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC5: End of Conversion Interrupt Disable 5

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC6: End of Conversion Interrupt Disable 6

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- EOC7: End of Conversion Interrupt Disable 7

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE0: Overrun Error Interrupt Disable 0

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE1: Overrun Error Interrupt Disable 1

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE2: Overrun Error Interrupt Disable 2

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE3: Overrun Error Interrupt Disable 3

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE4: Overrun Error Interrupt Disable 4

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE5: Overrun Error Interrupt Disable 5

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE6: Overrun Error Interrupt Disable 6

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE7: Overrun Error Interrupt Disable 7

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- DRDY: Data Ready Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- GOVRE: General Overrun Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ENDRX: End of Receive Buffer Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RXBUFF: Receive Buffer Full Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

#### ADC12B Interrupt Mask Register

Name: ADC12B_IMR

Access: read-only

Address: 0x400A802C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
OVRE7 | OVRE6 | OVRE5 | OVRE4 | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion Interrupt Mask 0

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC1: End of Conversion Interrupt Mask 1

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC2: End of Conversion Interrupt Mask 2

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC3: End of Conversion Interrupt Mask 3

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC4: End of Conversion Interrupt Mask 4

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC5: End of Conversion Interrupt Mask 5

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC6: End of Conversion Interrupt Mask 6

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- EOC7: End of Conversion Interrupt Mask 7

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE0: Overrun Error Interrupt Mask 0

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE1: Overrun Error Interrupt Mask 1

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE2: Overrun Error Interrupt Mask 2

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE3: Overrun Error Interrupt Mask 3

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE4: Overrun Error Interrupt Mask 4

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE5: Overrun Error Interrupt Mask 5

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE6: Overrun Error Interrupt Mask 6

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE7: Overrun Error Interrupt Mask 7

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- DRDY: Data Ready Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- GOVRE: General Overrun Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- ENDRX: End of Receive Buffer Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- RXBUFF: Receive Buffer Full Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

#### ADC12B Channel Data Register

Name: ADC12B_CDR[0:7]

Access: read-only

Address: 0x400A8030

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA

- DATA: Converted Data

-

#### ADC12B Analog Control Register

Name: ADC12B_ACR

Access: read-write

Address: 0x400A8064

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | OFFSET | DIFF
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | IBCTL
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | GAIN

- GAIN: Input Gain

  Value | Name | Description
  --- | --- | ---
  0x1 | - | 0.5
  0xB | - | 1
  0x66 | - | 2
  0x72 | - | 2

- IBCTL: Bias Current Control

  Value | Name | Description
  --- | --- | ---
  0x0 | - | typ - 20%
  0x1 | - | typ
  0x2 | - | typ + 20%
  0x3 | - | typ + 40%

- DIFF: Differential Mode

  Value | Name | Description
  --- | --- | ---
  0 | - | Single Ended Mode
  1 | - | Fully Differential Mode

- OFFSET: Input OFFSET

-

#### ADC12B Extended Mode Register

Name: ADC12B_EMR

Access: read-write

Address: 0x400A8068

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
OFF_MODE_STARTUP_TIME
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | OFFMODES

- OFFMODES: Off Mode if Sleep Bit (ADC12B_MR) = 1

  Value | Name | Description
  --- | --- | ---
  0 | - | Standby Mode
  1 | - | Off Mode

- OFF_MODE_STARTUP_TIME: Startup Time

-

#### ADC12B Receive Pointer Register

Name: ADC12B_RPR

Access: read-write

Address: 0x400A8100

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXPTR

- RXPTR: Receive Pointer Register

-

#### ADC12B Receive Counter Register

Name: ADC12B_RCR

Access: read-write

Address: 0x400A8104

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCTR

- RXCTR: Receive Counter Register

-

#### ADC12B Receive Next Pointer Register

Name: ADC12B_RNPR

Access: read-write

Address: 0x400A8110

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNPTR

- RXNPTR: Receive Next Pointer

-

#### ADC12B Receive Next Counter Register

Name: ADC12B_RNCR

Access: read-write

Address: 0x400A8114

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNCTR

- RXNCTR: Receive Next Counter

-

#### ADC12B Transfer Control Register

Name: ADC12B_PTCR

Access: write-only

Address: 0x400A8120

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TXTDIS | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RXTDIS | RXTEN

- RXTEN: Receiver Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables PDC receiver channel requests if RXTDIS is not set.

- RXTDIS: Receiver Transfer Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the PDC receiver channel requests.

- TXTEN: Transmitter Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the PDC transmitter channel requests.

- TXTDIS: Transmitter Transfer Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the PDC transmitter channel requests.

#### ADC12B Transfer Status Register

Name: ADC12B_PTSR

Access: read-only

Address: 0x400A8124

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RXTEN

- RXTEN: Receiver Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | PDC Receiver channel requests are disabled.
  1 | - | PDC Receiver channel requests are enabled.

- TXTEN: Transmitter Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | PDC Transmitter channel requests are disabled.
  1 | - | PDC Transmitter channel requests are enabled.