# SAM3N USART1

## Universal Synchronous Asynchronous Receiver Transmitter (USART1) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x40028000 | Control Register | USART1_CR | write-only | -
0x40028004 | Mode Register | USART1_MR | read-write | -
0x40028008 | Interrupt Enable Register | USART1_IER | write-only | -
0x4002800C | Interrupt Disable Register | USART1_IDR | write-only | -
0x40028010 | Interrupt Mask Register | USART1_IMR | read-only | 0x00000000
0x40028014 | Channel Status Register | USART1_CSR | read-only | -
0x40028018 | Receiver Holding Register | USART1_RHR | read-only | 0x00000000
0x4002801C | Transmitter Holding Register | USART1_THR | write-only | -
0x40028020 | Baud Rate Generator Register | USART1_BRGR | read-write | 0x00000000
0x40028024 | Receiver Time-out Register | USART1_RTOR | read-write | 0x00000000
0x40028028 | Transmitter Timeguard Register | USART1_TTGR | read-write | 0x00000000
0x40028040 | FI DI Ratio Register | USART1_FIDI | read-write | 0x00000174
0x40028044 | Number of Errors Register | USART1_NER | read-only | -
0x4002804C | IrDA Filter Register | USART1_IF | read-write | 0x00000000
0x400280E4 | Write Protect Mode Register | USART1_WPMR | read-write | 0x00000000
0x400280E8 | Write Protect Status Register | USART1_WPSR | read-only | 0x00000000

### Register Fields

#### USART1 Control Register

Name: USART1_CR

Access: write-only

Address: 0x40028000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RTSDIS | RTSEN | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RETTO | RSTNACK | RSTIT | SENDA | STTTO | STPBRK | STTBRK | RSTSTA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXDIS | TXEN | RXDIS | RXEN | RSTTX | RSTRX | - | -

- RSTRX: Reset Receiver

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets the receiver.

- RSTTX: Reset Transmitter

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets the transmitter.

- RXEN: Receiver Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the receiver, if RXDIS is 0.

- RXDIS: Receiver Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the receiver.

- TXEN: Transmitter Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the transmitter if TXDIS is 0.

- TXDIS: Transmitter Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the transmitter.

- RSTSTA: Reset Status Bits

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets the status bits PARE, FRAME, OVRE, UNRE and RXBRK in US_CSR.

- STTBRK: Start Break

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-mitted. No effect if a break is already being transmitted.

- STPBRK: Stop Break

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.

- STTTO: Start Time-out

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.

- SENDA: Send Address

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.

- RSTIT: Reset Iterations

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.

- RSTNACK: Reset Non Acknowledge

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect
  1 | - | Resets NACK in US_CSR.

- RETTO: Rearm Time-out

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect
  1 | - | Restart Time-out

- RTSEN: Request to Send Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Drives the pin RTS to 0.

- FCS: Force SPI Chip Select

-

- RTSDIS: Request to Send Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Drives the pin RTS to 1.

- RCS: Release SPI Chip Select

-

#### USART1 Mode Register

Name: USART1_MR

Access: read-write

Address: 0x40028004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | FILTER | - | MAX_ITERATION
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
INVDATA | - | DSNACK | INACK | OVER | CLKO | MODE9 | MSBF
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CHMODE | NBSTOP | PAR | SYNC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CHRL | USCLKS | USART_MODE

- USART_MODE

  Value | Name | Description
  --- | --- | ---
  0x0 | NORMAL | Normal mode
  0x1 | RS485 | RS485
  0x2 | HW_HANDSHAKING | Hardware Handshaking
  0x4 | IS07816_T_0 | IS07816 Protocol: T = 0
  0x6 | IS07816_T_1 | IS07816 Protocol: T = 1
  0x8 | IRDA | IrDA
  0xE | SPI_MASTER | SPI Master
  0xF | SPI_SLAVE | SPI Slave

- USCLKS: Clock Selection

  Value | Name | Description
  --- | --- | ---
  0x0 | MCK | Master Clock MCK is selected
  0x1 | DIV | Internal Clock Divided MCK/DIV (DIV=8) is selected
  0x3 | SCK | Serial Clock SLK is selected

- CHRL: Character Length.

  Value | Name | Description
  --- | --- | ---
  0x0 | 5_BIT | Character length is 5 bits
  0x1 | 6_BIT | Character length is 6 bits
  0x2 | 7_BIT | Character length is 7 bits
  0x3 | 8_BIT | Character length is 8 bits

- SYNC: Synchronous Mode Select

  Value | Name | Description
  --- | --- | ---
  0 | - | USART operates in Asynchronous Mode.
  1 | - | USART operates in Synchronous Mode.

- CPHA: SPI Clock Phase

-

- PAR: Parity Type

  Value | Name | Description
  --- | --- | ---
  0x0 | EVEN | Even parity
  0x1 | ODD | Odd parity
  0x2 | SPACE | Parity forced to 0 (Space)
  0x3 | MARK | Parity forced to 1 (Mark)
  0x4 | NO | No parity
  0x6 | MULTIDROP | Multidrop mode

- NBSTOP: Number of Stop Bits

  Value | Name | Description
  --- | --- | ---
  0x0 | 1_BIT | 1 stop bit
  0x1 | 1_5_BIT | 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
  0x2 | 2_BIT | 2 stop bits

- CHMODE: Channel Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | NORMAL | Normal Mode
  0x1 | AUTOMATIC | Automatic Echo. Receiver input is connected to the TXD pin.
  0x2 | LOCAL_LOOPBACK | Local Loopback. Transmitter output is connected to the Receiver Input.
  0x3 | REMOTE_LOOPBACK | Remote Loopback. RXD pin is internally connected to the TXD pin.

- MSBF: Bit Order

  Value | Name | Description
  --- | --- | ---
  0 | - | Least Significant Bit is sent/received first.
  1 | - | Most Significant Bit is sent/received first.

- CPOL: SPI Clock Polarity

-

- MODE9: 9-bit Character Length

  Value | Name | Description
  --- | --- | ---
  0 | - | CHRL defines character length.
  1 | - | 9-bit character length.

- CLKO: Clock Output Select

  Value | Name | Description
  --- | --- | ---
  0 | - | The USART does not drive the SCK pin.
  1 | - | The USART drives the SCK pin if USCLKS does not select the external clock SCK.

- OVER: Oversampling Mode

  Value | Name | Description
  --- | --- | ---
  0 | - | 16x Oversampling.
  1 | - | 8x Oversampling.

- INACK: Inhibit Non Acknowledge

  Value | Name | Description
  --- | --- | ---
  0 | - | The NACK is generated.
  1 | - | The NACK is not generated.

- DSNACK: Disable Successive NACK

  Value | Name | Description
  --- | --- | ---
  0 | - | NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
  1 | - | Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.

- INVDATA: INverted Data

  Value | Name | Description
  --- | --- | ---
  0 | - | The data field transmitted on TXD line is the same as the one written in US_THR register or the content read in US_RHR is the same as RXD line. Normal mode of operation.
  1 | - | The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR regis-ter or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted Mode of operation, useful for contactless card application. To be used with configuration bit MSBF.

- MAX_ITERATION

-

- FILTER: Infrared Receive Line Filter

  Value | Name | Description
  --- | --- | ---
  0 | - | The USART does not filter the receive line.
  1 | - | The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

#### USART1 Interrupt Enable Register

Name: USART1_IER

Access: write-only

Address: 0x40028008

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | CTSIC | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NACK | RXBUFF | TXBUFE | ITER | TXEMPTY | TIMEOUT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | RXBRK | TXRDY | RXRDY

- RXRDY: RXRDY Interrupt Enable

-

- TXRDY: TXRDY Interrupt Enable

-

- RXBRK: Receiver Break Interrupt Enable

-

- ENDRX: End of Receive Transfer Interrupt Enable

-

- ENDTX: End of Transmit Interrupt Enable

-

- OVRE: Overrun Error Interrupt Enable

-

- FRAME: Framing Error Interrupt Enable

-

- PARE: Parity Error Interrupt Enable

-

- TIMEOUT: Time-out Interrupt Enable

-

- TXEMPTY: TXEMPTY Interrupt Enable

-

- ITER: Max number of Repetitions Reached

-

- UNRE: SPI Underrun Error

-

- TXBUFE: Buffer Empty Interrupt Enable

-

- RXBUFF: Buffer Full Interrupt Enable

-

- NACK: Non AcknowledgeInterrupt Enable

-

- CTSIC: Clear to Send Input Change Interrupt Enable

-

#### USART1 Interrupt Disable Register

Name: USART1_IDR

Access: write-only

Address: 0x4002800C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | CTSIC | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NACK | RXBUFF | TXBUFE | ITER | TXEMPTY | TIMEOUT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | RXBRK | TXRDY | RXRDY

- RXRDY: RXRDY Interrupt Disable

-

- TXRDY: TXRDY Interrupt Disable

-

- RXBRK: Receiver Break Interrupt Disable

-

- ENDRX: End of Receive Transfer Interrupt Disable

-

- ENDTX: End of Transmit Interrupt Disable

-

- OVRE: Overrun Error Interrupt Disable

-

- FRAME: Framing Error Interrupt Disable

-

- PARE: Parity Error Interrupt Disable

-

- TIMEOUT: Time-out Interrupt Disable

-

- TXEMPTY: TXEMPTY Interrupt Disable

-

- ITER: Max number of Repetitions Reached Disable

-

- UNRE: SPI Underrun Error Disable

-

- TXBUFE: Buffer Empty Interrupt Disable

-

- RXBUFF: Buffer Full Interrupt Disable

-

- NACK: Non AcknowledgeInterrupt Disable

-

- CTSIC: Clear to Send Input Change Interrupt Disable

-

#### USART1 Interrupt Mask Register

Name: USART1_IMR

Access: read-only

Address: 0x40028010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | CTSIC | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NACK | RXBUFF | TXBUFE | ITER | TXEMPTY | TIMEOUT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | RXBRK | TXRDY | RXRDY

- RXRDY: RXRDY Interrupt Mask

-

- TXRDY: TXRDY Interrupt Mask

-

- RXBRK: Receiver Break Interrupt Mask

-

- ENDRX: End of Receive Transfer Interrupt Mask

-

- ENDTX: End of Transmit Interrupt Mask

-

- OVRE: Overrun Error Interrupt Mask

-

- FRAME: Framing Error Interrupt Mask

-

- PARE: Parity Error Interrupt Mask

-

- TIMEOUT: Time-out Interrupt Mask

-

- TXEMPTY: TXEMPTY Interrupt Mask

-

- ITER: Max number of Repetitions Reached Mask

-

- UNRE: SPI Underrun Error Mask

-

- TXBUFE: Buffer Empty Interrupt Mask

-

- RXBUFF: Buffer Full Interrupt Mask

-

- NACK: Non AcknowledgeInterrupt Mask

-

- CTSIC: Clear to Send Input Change Interrupt Mask

-

#### USART1 Channel Status Register

Name: USART1_CSR

Access: read-only

Address: 0x40028014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CTS | - | - | - | CTSIC | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NACK | RXBUFF | TXBUFE | ITER | TXEMPTY | TIMEOUT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | RXBRK | TXRDY | RXRDY

- RXRDY: Receiver Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
  1 | - | At least one complete character has been received and US_RHR has not yet been read.

- TXRDY: Transmitter Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
  1 | - | There is no character in the US_THR.

- RXBRK: Break Received/End of Break

  Value | Name | Description
  --- | --- | ---
  0 | - | No Break received or End of Break detected since the last RSTSTA.
  1 | - | Break Received or End of Break detected since the last RSTSTA.

- ENDRX: End of Receiver Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | The End of Transfer signal from the Receive PDC channel is inactive.
  1 | - | The End of Transfer signal from the Receive PDC channel is active.

- ENDTX: End of Transmitter Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | The End of Transfer signal from the Transmit PDC channel is inactive.
  1 | - | The End of Transfer signal from the Transmit PDC channel is active.

- OVRE: Overrun Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error has occurred since the last RSTSTA.
  1 | - | At least one overrun error has occurred since the last RSTSTA.

- FRAME: Framing Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No stop bit has been detected low since the last RSTSTA.
  1 | - | At least one stop bit has been detected low since the last RSTSTA.

- PARE: Parity Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No parity error has been detected since the last RSTSTA.
  1 | - | At least one parity error has been detected since the last RSTSTA.

- TIMEOUT: Receiver Time-out

  Value | Name | Description
  --- | --- | ---
  0 | - | There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
  1 | - | There has been a time-out since the last Start Time-out command (STTTO in US_CR).

- TXEMPTY: Transmitter Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
  1 | - | There are no characters in US_THR, nor in the Transmit Shift Register.

- ITER: Max number of Repetitions Reached

  Value | Name | Description
  --- | --- | ---
  0 | - | Maximum number of repetitions has not been reached since the last RSTSTA.
  1 | - | Maximum number of repetitions has been reached since the last RSTSTA.

- UNRE: SPI Underrun Error

-

- TXBUFE: Transmission Buffer Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | The signal Buffer Empty from the Transmit PDC channel is inactive.
  1 | - | The signal Buffer Empty from the Transmit PDC channel is active.

- RXBUFF: Reception Buffer Full

  Value | Name | Description
  --- | --- | ---
  0 | - | The signal Buffer Full from the Receive PDC channel is inactive.
  1 | - | The signal Buffer Full from the Receive PDC channel is active.

- NACK: Non AcknowledgeInterrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | Non Acknowledge has not been detected since the last RSTNACK.
  1 | - | At least one Non Acknowledge has been detected since the last RSTNACK.

- CTSIC: Clear to Send Input Change Flag

  Value | Name | Description
  --- | --- | ---
  0 | - | No input change has been detected on the CTS pin since the last read of US_CSR.
  1 | - | At least one input change has been detected on the CTS pin since the last read of US_CSR.

- CTS: Image of CTS Input

  Value | Name | Description
  --- | --- | ---
  0 | - | CTS is set to 0.
  1 | - | CTS is set to 1.

#### USART1 Receiver Holding Register

Name: USART1_RHR

Access: read-only

Address: 0x40028018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXSYNH | - | - | - | - | - | - | RXCHR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCHR

- RXCHR: Received Character

-

- RXSYNH: Received Sync

  Value | Name | Description
  --- | --- | ---
  0 | - | Last Character received is a Data.
  1 | - | Last Character received is a Command.

#### USART1 Transmitter Holding Register

Name: USART1_THR

Access: write-only

Address: 0x4002801C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXSYNH | - | - | - | - | - | - | TXCHR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCHR

- TXCHR: Character to be Transmitted

-

- TXSYNH: Sync Field to be transmitted

  Value | Name | Description
  --- | --- | ---
  0 | - | The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
  1 | - | The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.

#### USART1 Baud Rate Generator Register

Name: USART1_BRGR

Access: read-write

Address: 0x40028020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | FP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CD

- CD: Clock Divider

-

- FP: Fractional Part

-

#### USART1 Receiver Time-out Register

Name: USART1_RTOR

Access: read-write

Address: 0x40028024

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TO
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TO

- TO: Time-out Value

-

#### USART1 Transmitter Timeguard Register

Name: USART1_TTGR

Access: read-write

Address: 0x40028028

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TG

- TG: Timeguard Value

-

#### USART1 FI DI Ratio Register

Name: USART1_FIDI

Access: read-write

Address: 0x40028040

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | FI_DI_RATIO
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FI_DI_RATIO

- FI_DI_RATIO: FI Over DI Ratio Value

-

#### USART1 Number of Errors Register

Name: USART1_NER

Access: read-only

Address: 0x40028044

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NB_ERRORS

- NB_ERRORS: Number of Errors

-

#### USART1 IrDA Filter Register

Name: USART1_IF

Access: read-write

Address: 0x4002804C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IRDA_FILTER

- IRDA_FILTER: IrDA Filter

-

#### USART1 Write Protect Mode Register

Name: USART1_WPMR

Access: read-write

Address: 0x400280E4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WPKEY
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WPKEY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WPKEY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WPEN

- WPEN: Write Protect Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII).
  1 | - | Enables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII).

- WPKEY: Write Protect KEY

-

#### USART1 Write Protect Status Register

Name: USART1_WPSR

Access: read-only

Address: 0x400280E8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WPVSRC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WPVSRC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WPVS

- WPVS: Write Protect Violation Status

  Value | Name | Description
  --- | --- | ---
  0 | - | No Write Protect Violation has occurred since the last read of the US_WPSR register.
  1 | - | A Write Protect Violation has occurred since the last read of the US_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.

- WPVSRC: Write Protect Violation Source

-