SAM3S8 TC1

Timer Counter (TC1) User Interface

Registers

Register Mapping
Address Register Name Access Reset
0x40014000 Channel Control Register (channel = 0) TC1_CCR0 write-only -
0x40014004 Channel Mode Register (channel = 0) TC1_CMR0 read-write 0x00000000
0x40014008 Stepper Motor Mode Register (channel = 0) TC1_SMMR0 read-write 0x00000000
0x40014010 Counter Value (channel = 0) TC1_CV0 read-only 0x00000000
0x40014014 Register A (channel = 0) TC1_RA0 read-write 0x00000000
0x40014018 Register B (channel = 0) TC1_RB0 read-write 0x00000000
0x4001401C Register C (channel = 0) TC1_RC0 read-write 0x00000000
0x40014020 Status Register (channel = 0) TC1_SR0 read-only 0x00000000
0x40014024 Interrupt Enable Register (channel = 0) TC1_IER0 write-only -
0x40014028 Interrupt Disable Register (channel = 0) TC1_IDR0 write-only -
0x4001402C Interrupt Mask Register (channel = 0) TC1_IMR0 read-only 0x00000000
0x40014040 Channel Control Register (channel = 1) TC1_CCR1 write-only -
0x40014044 Channel Mode Register (channel = 1) TC1_CMR1 read-write 0x00000000
0x40014048 Stepper Motor Mode Register (channel = 1) TC1_SMMR1 read-write 0x00000000
0x40014050 Counter Value (channel = 1) TC1_CV1 read-only 0x00000000
0x40014054 Register A (channel = 1) TC1_RA1 read-write 0x00000000
0x40014058 Register B (channel = 1) TC1_RB1 read-write 0x00000000
0x4001405C Register C (channel = 1) TC1_RC1 read-write 0x00000000
0x40014060 Status Register (channel = 1) TC1_SR1 read-only 0x00000000
0x40014064 Interrupt Enable Register (channel = 1) TC1_IER1 write-only -
0x40014068 Interrupt Disable Register (channel = 1) TC1_IDR1 write-only -
0x4001406C Interrupt Mask Register (channel = 1) TC1_IMR1 read-only 0x00000000
0x40014080 Channel Control Register (channel = 2) TC1_CCR2 write-only -
0x40014084 Channel Mode Register (channel = 2) TC1_CMR2 read-write 0x00000000
0x40014088 Stepper Motor Mode Register (channel = 2) TC1_SMMR2 read-write 0x00000000
0x40014090 Counter Value (channel = 2) TC1_CV2 read-only 0x00000000
0x40014094 Register A (channel = 2) TC1_RA2 read-write 0x00000000
0x40014098 Register B (channel = 2) TC1_RB2 read-write 0x00000000
0x4001409C Register C (channel = 2) TC1_RC2 read-write 0x00000000
0x400140A0 Status Register (channel = 2) TC1_SR2 read-only 0x00000000
0x400140A4 Interrupt Enable Register (channel = 2) TC1_IER2 write-only -
0x400140A8 Interrupt Disable Register (channel = 2) TC1_IDR2 write-only -
0x400140AC Interrupt Mask Register (channel = 2) TC1_IMR2 read-only 0x00000000
0x400140C0 Block Control Register TC1_BCR write-only -
0x400140C4 Block Mode Register TC1_BMR read-write 0x00000000
0x400140C8 QDEC Interrupt Enable Register TC1_QIER write-only -
0x400140CC QDEC Interrupt Disable Register TC1_QIDR write-only -
0x400140D0 QDEC Interrupt Mask Register TC1_QIMR read-only 0x00000000
0x400140D4 QDEC Interrupt Status Register TC1_QISR read-only 0x00000000
0x400140D8 Fault Mode Register TC1_FMR read-write 0x00000000
0x400140E4 Write Protect Mode Register TC1_WPMR read-write 0x00000000

Register Fields

TC1 Channel Control Register (channel = 0)

Name: TC1_CCR0

Access: write-only

Address: 0x40014000

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN

TC1 Channel Mode Register (channel = 0)

Name: TC1_CMR0

Access: read-write

Address: 0x40014004

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS

Alternate: WAVE_EQ_1

31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS

TC1 Stepper Motor Mode Register (channel = 0)

Name: TC1_SMMR0

Access: read-write

Address: 0x40014008

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DOWN GCEN

TC1 Counter Value (channel = 0)

Name: TC1_CV0

Access: read-only

Address: 0x40014010

31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV

TC1 Register A (channel = 0)

Name: TC1_RA0

Access: read-write

Address: 0x40014014

31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA

TC1 Register B (channel = 0)

Name: TC1_RB0

Access: read-write

Address: 0x40014018

31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB

TC1 Register C (channel = 0)

Name: TC1_RC0

Access: read-write

Address: 0x4001401C

31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC

TC1 Status Register (channel = 0)

Name: TC1_SR0

Access: read-only

Address: 0x40014020

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Enable Register (channel = 0)

Name: TC1_IER0

Access: write-only

Address: 0x40014024

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Disable Register (channel = 0)

Name: TC1_IDR0

Access: write-only

Address: 0x40014028

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Mask Register (channel = 0)

Name: TC1_IMR0

Access: read-only

Address: 0x4001402C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Channel Control Register (channel = 1)

Name: TC1_CCR1

Access: write-only

Address: 0x40014040

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN

TC1 Channel Mode Register (channel = 1)

Name: TC1_CMR1

Access: read-write

Address: 0x40014044

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS

Alternate: WAVE_EQ_1

31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS

TC1 Stepper Motor Mode Register (channel = 1)

Name: TC1_SMMR1

Access: read-write

Address: 0x40014048

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DOWN GCEN

TC1 Counter Value (channel = 1)

Name: TC1_CV1

Access: read-only

Address: 0x40014050

31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV

TC1 Register A (channel = 1)

Name: TC1_RA1

Access: read-write

Address: 0x40014054

31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA

TC1 Register B (channel = 1)

Name: TC1_RB1

Access: read-write

Address: 0x40014058

31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB

TC1 Register C (channel = 1)

Name: TC1_RC1

Access: read-write

Address: 0x4001405C

31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC

TC1 Status Register (channel = 1)

Name: TC1_SR1

Access: read-only

Address: 0x40014060

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Enable Register (channel = 1)

Name: TC1_IER1

Access: write-only

Address: 0x40014064

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Disable Register (channel = 1)

Name: TC1_IDR1

Access: write-only

Address: 0x40014068

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Mask Register (channel = 1)

Name: TC1_IMR1

Access: read-only

Address: 0x4001406C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Channel Control Register (channel = 2)

Name: TC1_CCR2

Access: write-only

Address: 0x40014080

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN

TC1 Channel Mode Register (channel = 2)

Name: TC1_CMR2

Access: read-write

Address: 0x40014084

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS

Alternate: WAVE_EQ_1

31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS

TC1 Stepper Motor Mode Register (channel = 2)

Name: TC1_SMMR2

Access: read-write

Address: 0x40014088

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DOWN GCEN

TC1 Counter Value (channel = 2)

Name: TC1_CV2

Access: read-only

Address: 0x40014090

31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV

TC1 Register A (channel = 2)

Name: TC1_RA2

Access: read-write

Address: 0x40014094

31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA

TC1 Register B (channel = 2)

Name: TC1_RB2

Access: read-write

Address: 0x40014098

31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB

TC1 Register C (channel = 2)

Name: TC1_RC2

Access: read-write

Address: 0x4001409C

31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC

TC1 Status Register (channel = 2)

Name: TC1_SR2

Access: read-only

Address: 0x400140A0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Enable Register (channel = 2)

Name: TC1_IER2

Access: write-only

Address: 0x400140A4

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Disable Register (channel = 2)

Name: TC1_IDR2

Access: write-only

Address: 0x400140A8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Interrupt Mask Register (channel = 2)

Name: TC1_IMR2

Access: read-only

Address: 0x400140AC

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC1 Block Control Register

Name: TC1_BCR

Access: write-only

Address: 0x400140C0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - SYNC

TC1 Block Mode Register

Name: TC1_BMR

Access: read-write

Address: 0x400140C4

31 30 29 28 27 26 25 24
- - - - - - MAXFILT
23 22 21 20 19 18 17 16
MAXFILT FILTER - IDXPHB SWAP
15 14 13 12 11 10 9 8
INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN
7 6 5 4 3 2 1 0
- - TC2XC2S TC1XC1S TC0XC0S

TC1 QDEC Interrupt Enable Register

Name: TC1_QIER

Access: write-only

Address: 0x400140C8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC1 QDEC Interrupt Disable Register

Name: TC1_QIDR

Access: write-only

Address: 0x400140CC

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC1 QDEC Interrupt Mask Register

Name: TC1_QIMR

Access: read-only

Address: 0x400140D0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC1 QDEC Interrupt Status Register

Name: TC1_QISR

Access: read-only

Address: 0x400140D4

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - DIR
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC1 Fault Mode Register

Name: TC1_FMR

Access: read-write

Address: 0x400140D8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - ENCF1 ENCF0

TC1 Write Protect Mode Register

Name: TC1_WPMR

Access: read-write

Address: 0x400140E4

31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7 6 5 4 3 2 1 0
- - - - - - - WPEN