SAM3S TWI1

Two-wire Interface (TWI1) User Interface

Registers

Register Mapping
Address Register Name Access Reset
0x4001C000 Control Register TWI1_CR write-only -
0x4001C004 Master Mode Register TWI1_MMR read-write 0x00000000
0x4001C008 Slave Mode Register TWI1_SMR read-write 0x00000000
0x4001C00C Internal Address Register TWI1_IADR read-write 0x00000000
0x4001C010 Clock Waveform Generator Register TWI1_CWGR read-write 0x00000000
0x4001C020 Status Register TWI1_SR read-only 0x0000F009
0x4001C024 Interrupt Enable Register TWI1_IER write-only -
0x4001C028 Interrupt Disable Register TWI1_IDR write-only -
0x4001C02C Interrupt Mask Register TWI1_IMR read-only 0x00000000
0x4001C030 Receive Holding Register TWI1_RHR read-only 0x00000000
0x4001C034 Transmit Holding Register TWI1_THR write-only 0x00000000
0x4001C100 Receive Pointer Register TWI1_RPR read-write 0x00000000
0x4001C104 Receive Counter Register TWI1_RCR read-write 0x00000000
0x4001C108 Transmit Pointer Register TWI1_TPR read-write 0x00000000
0x4001C10C Transmit Counter Register TWI1_TCR read-write 0x00000000
0x4001C110 Receive Next Pointer Register TWI1_RNPR read-write 0x00000000
0x4001C114 Receive Next Counter Register TWI1_RNCR read-write 0x00000000
0x4001C118 Transmit Next Pointer Register TWI1_TNPR read-write 0x00000000
0x4001C11C Transmit Next Counter Register TWI1_TNCR read-write 0x00000000
0x4001C120 Transfer Control Register TWI1_PTCR write-only 0x00000000
0x4001C124 Transfer Status Register TWI1_PTSR read-only 0x00000000

Register Fields

TWI1 Control Register

Name: TWI1_CR

Access: write-only

Address: 0x4001C000

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
SWRST QUICK SVDIS SVEN MSDIS MSEN STOP START

TWI1 Master Mode Register

Name: TWI1_MMR

Access: read-write

Address: 0x4001C004

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- DADR
15 14 13 12 11 10 9 8
- - - MREAD - - IADRSZ
7 6 5 4 3 2 1 0
- - - - - - - -

TWI1 Slave Mode Register

Name: TWI1_SMR

Access: read-write

Address: 0x4001C008

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- SADR
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -

TWI1 Internal Address Register

Name: TWI1_IADR

Access: read-write

Address: 0x4001C00C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
IADR
15 14 13 12 11 10 9 8
IADR
7 6 5 4 3 2 1 0
IADR

TWI1 Clock Waveform Generator Register

Name: TWI1_CWGR

Access: read-write

Address: 0x4001C010

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - CKDIV
15 14 13 12 11 10 9 8
CHDIV
7 6 5 4 3 2 1 0
CLDIV

TWI1 Status Register

Name: TWI1_SR

Access: read-only

Address: 0x4001C020

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK
7 6 5 4 3 2 1 0
- OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP

TWI1 Interrupt Enable Register

Name: TWI1_IER

Access: write-only

Address: 0x4001C024

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
7 6 5 4 3 2 1 0
- OVRE GACC SVACC - TXRDY RXRDY TXCOMP

TWI1 Interrupt Disable Register

Name: TWI1_IDR

Access: write-only

Address: 0x4001C028

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
7 6 5 4 3 2 1 0
- OVRE GACC SVACC - TXRDY RXRDY TXCOMP

TWI1 Interrupt Mask Register

Name: TWI1_IMR

Access: read-only

Address: 0x4001C02C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
7 6 5 4 3 2 1 0
- OVRE GACC SVACC - TXRDY RXRDY TXCOMP

TWI1 Receive Holding Register

Name: TWI1_RHR

Access: read-only

Address: 0x4001C030

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
RXDATA

TWI1 Transmit Holding Register

Name: TWI1_THR

Access: write-only

Address: 0x4001C034

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
TXDATA

TWI1 Receive Pointer Register

Name: TWI1_RPR

Access: read-write

Address: 0x4001C100

31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
7 6 5 4 3 2 1 0
RXPTR

TWI1 Receive Counter Register

Name: TWI1_RCR

Access: read-write

Address: 0x4001C104

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RXCTR
7 6 5 4 3 2 1 0
RXCTR

TWI1 Transmit Pointer Register

Name: TWI1_TPR

Access: read-write

Address: 0x4001C108

31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
7 6 5 4 3 2 1 0
TXPTR

TWI1 Transmit Counter Register

Name: TWI1_TCR

Access: read-write

Address: 0x4001C10C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TXCTR
7 6 5 4 3 2 1 0
TXCTR

TWI1 Receive Next Pointer Register

Name: TWI1_RNPR

Access: read-write

Address: 0x4001C110

31 30 29 28 27 26 25 24
RXNPTR
23 22 21 20 19 18 17 16
RXNPTR
15 14 13 12 11 10 9 8
RXNPTR
7 6 5 4 3 2 1 0
RXNPTR

TWI1 Receive Next Counter Register

Name: TWI1_RNCR

Access: read-write

Address: 0x4001C114

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RXNCTR
7 6 5 4 3 2 1 0
RXNCTR

TWI1 Transmit Next Pointer Register

Name: TWI1_TNPR

Access: read-write

Address: 0x4001C118

31 30 29 28 27 26 25 24
TXNPTR
23 22 21 20 19 18 17 16
TXNPTR
15 14 13 12 11 10 9 8
TXNPTR
7 6 5 4 3 2 1 0
TXNPTR

TWI1 Transmit Next Counter Register

Name: TWI1_TNCR

Access: read-write

Address: 0x4001C11C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TXNCTR
7 6 5 4 3 2 1 0
TXNCTR

TWI1 Transfer Control Register

Name: TWI1_PTCR

Access: write-only

Address: 0x4001C120

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - TXTDIS TXTEN
7 6 5 4 3 2 1 0
- - - - - - RXTDIS RXTEN

TWI1 Transfer Status Register

Name: TWI1_PTSR

Access: read-only

Address: 0x4001C124

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - TXTEN
7 6 5 4 3 2 1 0
- - - - - - - RXTEN