2011-10-25 15:52:09 +02:00
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/*! \file *********************************************************************
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*
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* \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller.
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*
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* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* - Compiler: IAR EWARM and CodeSourcery GCC for ARM
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* - Supported devices: All SAM devices with a Analog-to-Digital Converter can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.com/
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*
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*******************************************************************************/
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2011-11-17 16:56:47 +01:00
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#include "../chip.h"
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2011-10-25 15:52:09 +02:00
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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2011-11-17 16:56:47 +01:00
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#endif /* __cplusplus */
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2011-10-25 15:52:09 +02:00
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/**INDENT-ON**/
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/// @endcond
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2012-03-27 12:03:40 +02:00
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#if SAM3U_SERIES
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Initializes the given ADC with the specified ADC clock and startup time.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param dw_mck Main clock of the device (value in Hz).
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* \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz).
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* \param ul_startuptime ADC start up time value(value in us). Please refer to the product datasheet for details.
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* \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details.
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*
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* \retval 0 The initialization operation succeeds.
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* \retval others The initialization operation fails.
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*/
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2011-11-17 16:56:47 +01:00
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uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime)
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2011-10-25 15:52:09 +02:00
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{
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p_adc->ADC_CR = ADC_CR_SWRST;
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/* Reset Mode Register */
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p_adc->ADC_MR = 0;
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/* Reset PDC transfer */
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p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS);
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p_adc->ADC_RCR = 0;
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p_adc->ADC_RNCR = 0;
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2011-11-27 19:15:33 +01:00
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uint32_t prescal = ul_mck/(2 * ul_adc_clock) - 1;
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// check for rounding errors
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if ( (ul_mck/((prescal+1)*2)) > ul_adc_clock ) {
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prescal++;
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ul_adc_clock = ul_mck/((prescal+1)*2);
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}
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uint32_t startup = ((ul_adc_clock/1000000) * ul_startuptime / 8) - 1;
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p_adc->ADC_MR |= ADC_MR_PRESCAL(prescal) | ADC_MR_STARTUP(startup);
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2011-10-25 15:52:09 +02:00
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return 0;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Configures conversion resolution.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param resolution ADC resolution.
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*/
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void adc_set_resolution(Adc *p_adc, adc_resolution_t resolution)
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{
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p_adc->ADC_MR |= (resolution<<4) & ADC_MR_LOWRES;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Configures conversion trigger and free run mode.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param trigger Conversion trigger.
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*/
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void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger)
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{
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p_adc->ADC_MR |= trigger;
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}
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/**
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* \brief Configures ADC power saving mode.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions
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* ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions
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* \param uc_offmode 0 Standby Mode (if Sleep Bit = 1)
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* 1 Off Mode
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*/
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void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_offmode)
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{
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p_adc->ADC_MR |= ((uc_sleep<<5) & ADC_MR_SLEEP) ;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Configures ADC timing.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param ul_sh ADC sample and hold time = uc_sh / ADC clock.
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*/
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void adc_configure_timing(Adc *p_adc, uint32_t ul_sh)
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{
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p_adc->ADC_MR |= ADC_MR_SHTIM( ul_sh ) ;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Starts analog-to-digital conversion.
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*
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* \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion.
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*
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* \param p_adc Pointer to an ADC instance.
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*/
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void adc_start(Adc *p_adc)
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{
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p_adc->ADC_CR = ADC_CR_START;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Stop analog-to-digital conversion.
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* \param p_adc Pointer to an ADC instance.
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*/
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void adc_stop(Adc *p_adc)
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{
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p_adc->ADC_CR = ADC_CR_SWRST;
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}
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/**
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* \brief Enables the specified ADC channel.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param adc_ch ADC channel number.
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*/
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void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
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{
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p_adc->ADC_CHER = 1 << adc_ch;
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}
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/**
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* \brief Disables the specified ADC channel.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param adc_ch ADC channel number.
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*/
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void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
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{
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p_adc->ADC_CHDR = 1 << adc_ch;
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}
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/**
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* \brief Reads the ADC channel status.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param adc_ch ADC channel number.
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*
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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2011-11-21 12:16:54 +01:00
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uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch)
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2011-10-25 15:52:09 +02:00
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{
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return p_adc->ADC_CHSR & (1 << adc_ch);
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}
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2011-11-21 12:16:54 +01:00
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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uint32_t adc_get_status(Adc *p_adc)
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{
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return p_adc->ADC_SR;
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}
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Reads the ADC result data of the specified channel.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param adc_ch ADC channel number.
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*
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* \retval ADC data of the specified channel.
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*/
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uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch)
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{
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uint32_t dwData = 0;
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if ( 15 >= adc_ch )
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{
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dwData=*(p_adc->ADC_CDR+adc_ch) ;
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}
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return dwData ;
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}
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/**
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* \brief Reads the last ADC result data.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC data.
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*/
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uint32_t adc_get_latest_value(Adc *p_adc)
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{
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return p_adc->ADC_LCDR;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Returns the actual ADC clock.
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*
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* \param p_adc Pointer to an ADC instance.
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* \param ul_mck Main clock of the device (value in Hz).
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*
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* \retval 0 The actual ADC clock (value in Hz).
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*/
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uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck)
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{
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uint32_t ul_adcfreq;
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uint32_t ul_prescal;
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/* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
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ul_prescal = (( p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos);
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ul_adcfreq = ul_mck / ((ul_prescal+1)*2);
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return ul_adcfreq;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Enables ADC interrupt(s).
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*
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* \param p_adc Pointer to an ADC instance.
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* \param dw_source Interrupt(s) to be enabled.
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*/
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void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source)
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{
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p_adc->ADC_IER = ul_source;
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}
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/**
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* \brief Disables ADC interrupt(s).
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*
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* \param p_adc Pointer to an ADC instance.
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* \param dw_source Interrupt(s) to be disabled.
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*/
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void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source)
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{
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p_adc->ADC_IDR = ul_source;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Reads ADC interrupt mask.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC interrupt status.
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*/
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uint32_t adc_get_interrupt_status(Adc *p_adc)
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{
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return p_adc->ADC_SR ;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/** \brief Read ADC interrupt mask.
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*
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* \param p_uart pointer to a UART instance.
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*
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* \return The interrupt mask value.
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*/
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uint32_t adc_get_interrupt_mask(Adc *p_adc)
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{
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return p_adc->ADC_IMR;
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Reads overrun status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC overrun status.
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*/
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uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch)
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{
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return p_adc->ADC_SR & (0x01u << (adc_ch+8));
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}
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2011-11-17 16:56:47 +01:00
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2011-10-25 15:52:09 +02:00
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/**
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* \brief Gets PDC registers base address.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval PDC registers base for PDC driver to access.
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*/
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Pdc *adc_get_pdc_base(Adc *p_adc)
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{
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return PDC_ADC;
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}
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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2011-11-17 16:56:47 +01:00
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#endif /* __cplusplus */
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2011-10-25 15:52:09 +02:00
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/**INDENT-ON**/
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/// @endcond
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2012-03-27 12:03:40 +02:00
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#endif /* SAM3U_SERIES */
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