2011-09-06 21:05:41 +02:00
|
|
|
/* $asf_license$ */
|
2011-09-05 22:59:49 +02:00
|
|
|
|
|
|
|
|
#ifndef _SAM3U_RTC_COMPONENT_
|
|
|
|
|
#define _SAM3U_RTC_COMPONENT_
|
|
|
|
|
|
|
|
|
|
/* ============================================================================= */
|
|
|
|
|
/** SOFTWARE API DEFINITION FOR Real-time Clock */
|
|
|
|
|
/* ============================================================================= */
|
|
|
|
|
/** \addtogroup SAM3U_RTC Real-time Clock */
|
|
|
|
|
/*@{*/
|
|
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
/** \brief Rtc hardware registers */
|
|
|
|
|
typedef struct {
|
|
|
|
|
RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
|
|
|
|
|
RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
|
|
|
|
|
RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
|
|
|
|
|
RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
|
|
|
|
|
RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
|
|
|
|
|
RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
|
|
|
|
|
RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
|
|
|
|
|
WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
|
|
|
|
|
WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
|
|
|
|
|
WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
|
|
|
|
|
RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
|
|
|
|
|
RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
|
|
|
|
|
RoReg Reserved1[45];
|
|
|
|
|
RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
|
|
|
|
|
} Rtc;
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
|
|
|
|
|
#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
|
|
|
|
|
#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
|
|
|
|
|
#define RTC_CR_TIMEVSEL_Pos 8
|
|
|
|
|
#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
|
|
|
|
|
#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
|
|
|
|
|
#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
|
|
|
|
|
#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
|
|
|
|
|
#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
|
|
|
|
|
#define RTC_CR_CALEVSEL_Pos 16
|
|
|
|
|
#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
|
|
|
|
|
#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
|
|
|
|
|
#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
|
|
|
|
|
#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
|
|
|
|
|
/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
|
|
|
|
|
#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
|
|
|
|
|
/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
|
|
|
|
|
#define RTC_TIMR_SEC_Pos 0
|
|
|
|
|
#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
|
|
|
|
|
#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
|
|
|
|
|
#define RTC_TIMR_MIN_Pos 8
|
|
|
|
|
#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
|
|
|
|
|
#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
|
|
|
|
|
#define RTC_TIMR_HOUR_Pos 16
|
|
|
|
|
#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
|
|
|
|
|
#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
|
|
|
|
|
#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
|
|
|
|
|
/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
|
|
|
|
|
#define RTC_CALR_CENT_Pos 0
|
|
|
|
|
#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
|
|
|
|
|
#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
|
|
|
|
|
#define RTC_CALR_YEAR_Pos 8
|
|
|
|
|
#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
|
|
|
|
|
#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
|
|
|
|
|
#define RTC_CALR_MONTH_Pos 16
|
|
|
|
|
#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
|
|
|
|
|
#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
|
|
|
|
|
#define RTC_CALR_DAY_Pos 21
|
|
|
|
|
#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
|
|
|
|
|
#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
|
|
|
|
|
#define RTC_CALR_DATE_Pos 24
|
|
|
|
|
#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
|
|
|
|
|
#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
|
|
|
|
|
/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
|
|
|
|
|
#define RTC_TIMALR_SEC_Pos 0
|
|
|
|
|
#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
|
|
|
|
|
#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
|
|
|
|
|
#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
|
|
|
|
|
#define RTC_TIMALR_MIN_Pos 8
|
|
|
|
|
#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
|
|
|
|
|
#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
|
|
|
|
|
#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
|
|
|
|
|
#define RTC_TIMALR_HOUR_Pos 16
|
|
|
|
|
#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
|
|
|
|
|
#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
|
|
|
|
|
#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
|
|
|
|
|
#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
|
|
|
|
|
/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
|
|
|
|
|
#define RTC_CALALR_MONTH_Pos 16
|
|
|
|
|
#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
|
|
|
|
|
#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
|
|
|
|
|
#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
|
|
|
|
|
#define RTC_CALALR_DATE_Pos 24
|
|
|
|
|
#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
|
|
|
|
|
#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
|
|
|
|
|
#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
|
|
|
|
|
/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
|
|
|
|
|
#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
|
|
|
|
|
#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
|
|
|
|
|
#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
|
|
|
|
|
#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
|
|
|
|
|
#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
|
|
|
|
|
/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
|
|
|
|
|
#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
|
|
|
|
|
#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
|
|
|
|
|
#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
|
|
|
|
|
#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
|
|
|
|
|
#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
|
|
|
|
|
/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
|
|
|
|
|
#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
|
|
|
|
|
#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
|
|
|
|
|
#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
|
|
|
|
|
#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
|
|
|
|
|
#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
|
|
|
|
|
/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
|
|
|
|
|
#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
|
|
|
|
|
#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
|
|
|
|
|
#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
|
|
|
|
|
#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
|
|
|
|
|
#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
|
|
|
|
|
/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
|
|
|
|
|
#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
|
|
|
|
|
#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
|
|
|
|
|
#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
|
|
|
|
|
#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
|
|
|
|
|
#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
|
|
|
|
|
/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
|
|
|
|
|
#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
|
|
|
|
|
#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
|
|
|
|
|
#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
|
|
|
|
|
#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
|
|
|
|
|
/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
|
|
|
|
|
#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
|
|
|
|
|
#define RTC_WPMR_WPKEY_Pos 8
|
|
|
|
|
#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */
|
|
|
|
|
#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
|
|
|
|
|
|
|
|
|
|
/*@}*/
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#endif /* _SAM3U_RTC_COMPONENT_ */
|
