2011-09-06 21:05:41 +02:00
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/* $asf_license$ */
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2011-09-05 22:59:49 +02:00
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#ifndef _SAM3U_RTC_INSTANCE_
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#define _SAM3U_RTC_INSTANCE_
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/* ========== Register definition for RTC peripheral ========== */
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2011-09-06 21:05:41 +02:00
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#ifdef __ASSEMBLY__
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#define REG_RTC_CR (0x400E1260U) /**< \brief (RTC) Control Register */
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#define REG_RTC_MR (0x400E1264U) /**< \brief (RTC) Mode Register */
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#define REG_RTC_TIMR (0x400E1268U) /**< \brief (RTC) Time Register */
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#define REG_RTC_CALR (0x400E126CU) /**< \brief (RTC) Calendar Register */
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#define REG_RTC_TIMALR (0x400E1270U) /**< \brief (RTC) Time Alarm Register */
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#define REG_RTC_CALALR (0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
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#define REG_RTC_SR (0x400E1278U) /**< \brief (RTC) Status Register */
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#define REG_RTC_SCCR (0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
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#define REG_RTC_IER (0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR (0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR (0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
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#define REG_RTC_VER (0x400E128CU) /**< \brief (RTC) Valid Entry Register */
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#define REG_RTC_WPMR (0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
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#else
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#define REG_RTC_CR (*(RwReg*)0x400E1260U) /**< \brief (RTC) Control Register */
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#define REG_RTC_MR (*(RwReg*)0x400E1264U) /**< \brief (RTC) Mode Register */
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#define REG_RTC_TIMR (*(RwReg*)0x400E1268U) /**< \brief (RTC) Time Register */
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#define REG_RTC_CALR (*(RwReg*)0x400E126CU) /**< \brief (RTC) Calendar Register */
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#define REG_RTC_TIMALR (*(RwReg*)0x400E1270U) /**< \brief (RTC) Time Alarm Register */
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#define REG_RTC_CALALR (*(RwReg*)0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
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#define REG_RTC_SR (*(RoReg*)0x400E1278U) /**< \brief (RTC) Status Register */
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#define REG_RTC_SCCR (*(WoReg*)0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
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#define REG_RTC_IER (*(WoReg*)0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR (*(WoReg*)0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR (*(RoReg*)0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
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#define REG_RTC_VER (*(RoReg*)0x400E128CU) /**< \brief (RTC) Valid Entry Register */
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#define REG_RTC_WPMR (*(RwReg*)0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
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#endif /* __ASSEMBLY__ */
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2011-09-05 22:59:49 +02:00
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#endif /* _SAM3U_RTC_INSTANCE_ */
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