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30 lines
2.2 KiB
C
30 lines
2.2 KiB
C
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/* %ATMEL_LICENCE% */
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#ifndef _SAM3S8_SPI_INSTANCE_
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#define _SAM3S8_SPI_INSTANCE_
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/* ========== Register definition for SPI peripheral ========== */
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#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
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#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
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#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
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#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
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#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
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#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
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#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
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#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
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#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
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#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
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#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
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#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */
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#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */
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#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
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#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
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#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
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#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
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#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
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#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
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#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */
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#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */
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#endif /* _SAM3S8_SPI_INSTANCE_ */
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