2011-09-06 21:05:41 +02:00
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/* $asf_license$ */
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2011-09-05 22:59:49 +02:00
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#ifndef _SAM3XA_DACC_INSTANCE_
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#define _SAM3XA_DACC_INSTANCE_
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/* ========== Register definition for DACC peripheral ========== */
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2011-09-06 21:05:41 +02:00
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#ifdef __ASSEMBLY__
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#define REG_DACC_CR (0x400C8000U) /**< \brief (DACC) Control Register */
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#define REG_DACC_MR (0x400C8004U) /**< \brief (DACC) Mode Register */
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#define REG_DACC_CHER (0x400C8010U) /**< \brief (DACC) Channel Enable Register */
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#define REG_DACC_CHDR (0x400C8014U) /**< \brief (DACC) Channel Disable Register */
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#define REG_DACC_CHSR (0x400C8018U) /**< \brief (DACC) Channel Status Register */
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#define REG_DACC_CDR (0x400C8020U) /**< \brief (DACC) Conversion Data Register */
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#define REG_DACC_IER (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
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#define REG_DACC_IDR (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
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#define REG_DACC_IMR (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
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#define REG_DACC_ISR (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
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#define REG_DACC_ACR (0x400C8094U) /**< \brief (DACC) Analog Current Register */
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#define REG_DACC_WPMR (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
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#define REG_DACC_WPSR (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
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#define REG_DACC_RPR (0x400C8100U) /**< \brief (DACC) Receive Pointer Register */
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#define REG_DACC_RCR (0x400C8104U) /**< \brief (DACC) Receive Counter Register */
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#define REG_DACC_TPR (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
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#define REG_DACC_TCR (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
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#define REG_DACC_RNPR (0x400C8110U) /**< \brief (DACC) Receive Next Pointer Register */
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#define REG_DACC_RNCR (0x400C8114U) /**< \brief (DACC) Receive Next Counter Register */
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#define REG_DACC_TNPR (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
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#define REG_DACC_TNCR (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
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#define REG_DACC_PTCR (0x400C8120U) /**< \brief (DACC) Transfer Control Register */
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#define REG_DACC_PTSR (0x400C8124U) /**< \brief (DACC) Transfer Status Register */
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#else
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#define REG_DACC_CR (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */
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#define REG_DACC_MR (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */
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#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */
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#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */
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#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */
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#define REG_DACC_CDR (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */
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#define REG_DACC_IER (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
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#define REG_DACC_IDR (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
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#define REG_DACC_IMR (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
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#define REG_DACC_ISR (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
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#define REG_DACC_ACR (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */
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#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
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#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
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#define REG_DACC_RPR (*(RwReg*)0x400C8100U) /**< \brief (DACC) Receive Pointer Register */
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#define REG_DACC_RCR (*(RwReg*)0x400C8104U) /**< \brief (DACC) Receive Counter Register */
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#define REG_DACC_TPR (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
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#define REG_DACC_TCR (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
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#define REG_DACC_RNPR (*(RwReg*)0x400C8110U) /**< \brief (DACC) Receive Next Pointer Register */
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#define REG_DACC_RNCR (*(RwReg*)0x400C8114U) /**< \brief (DACC) Receive Next Counter Register */
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#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
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#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
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#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */
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#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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2011-09-05 22:59:49 +02:00
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#endif /* _SAM3XA_DACC_INSTANCE_ */
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