2011-09-06 21:05:41 +02:00
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/* $asf_license$ */
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2011-09-05 22:59:49 +02:00
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#ifndef _SAM3XA_SDRAMC_INSTANCE_
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#define _SAM3XA_SDRAMC_INSTANCE_
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/* ========== Register definition for SDRAMC peripheral ========== */
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2011-09-06 21:05:41 +02:00
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#ifdef __ASSEMBLY__
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#define REG_SDRAMC_MR (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
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#define REG_SDRAMC_TR (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
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#define REG_SDRAMC_CR (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
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#define REG_SDRAMC_LPR (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
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#define REG_SDRAMC_IER (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
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#define REG_SDRAMC_IDR (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
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#define REG_SDRAMC_IMR (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
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#define REG_SDRAMC_ISR (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
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#define REG_SDRAMC_MDR (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
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#define REG_SDRAMC_CR1 (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
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#define REG_SDRAMC_OCMS (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
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#else
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#define REG_SDRAMC_MR (*(RwReg*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
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#define REG_SDRAMC_TR (*(RwReg*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
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#define REG_SDRAMC_CR (*(RwReg*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
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#define REG_SDRAMC_LPR (*(RwReg*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
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#define REG_SDRAMC_IER (*(WoReg*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
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#define REG_SDRAMC_IDR (*(WoReg*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
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#define REG_SDRAMC_IMR (*(RoReg*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
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#define REG_SDRAMC_ISR (*(RoReg*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
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#define REG_SDRAMC_MDR (*(RwReg*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
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#define REG_SDRAMC_CR1 (*(RwReg*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
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#define REG_SDRAMC_OCMS (*(RwReg*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
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#endif /* __ASSEMBLY__ */
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2011-09-05 22:59:49 +02:00
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#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
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