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79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
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/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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/*! \page License
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* Copyright (C) 2009, H&D Wireless AB All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of H&D Wireless AB may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CLOCKS_H
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#define CLOCKS_H
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#include "board.h"
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#if BOARD == EVK1100
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# define USE_PLL
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# define OSC 0
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# define PLL_MUL 10
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#elif BOARD == EVK1101
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# define USE_PLL
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# define OSC 0
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# define PLL_MUL 9
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#elif BOARD == EVK1104
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# define USE_PLL
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# define OSC 0
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# define PLL_MUL 9 /* for some reason we cant use 66 MHz */
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#elif BOARD == EVK1105
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# define USE_PLL
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# define OSC 1
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# define PLL_MUL 10
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#elif BOARD == ARDUINO
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# define USE_PLL
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# define OSC 0
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# define PLL_MUL 8
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#endif
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#if OSC == 0
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# define FOSC FOSC0 /* 12 MHz */
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#else
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# define FOSC FOSC1 /* 11.2896 MHz */
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#endif
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#ifdef USE_PLL
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# define FMCK_HZ ((FOSC * (PLL_MUL + 1)) / 2)
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#else
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# define FMCK_HZ FOSC
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#endif
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#define FCPU_HZ FMCK_HZ
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#define FHSB_HZ FCPU_HZ
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#define FPBB_HZ FMCK_HZ
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#define FPBA_HZ FMCK_HZ
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void init_sys_clocks(void);
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#endif
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