2009-06-01 10:32:11 +02:00
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/*
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HardwareSerial.cpp - Hardware serial library for Wiring
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Copyright (c) 2006 Nicholas Zambetti. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Modified 23 November 2006 by David A. Mellis
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2010-10-17 19:36:02 +02:00
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Modified 28 September 2010 by Mark Sproul
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2012-08-14 15:50:36 +02:00
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Modified 14 August 2012 by Alarus
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2009-06-01 10:32:11 +02:00
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*/
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2010-07-05 01:22:34 +02:00
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#include <stdlib.h>
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2009-06-01 10:32:11 +02:00
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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2011-03-02 02:00:16 +01:00
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#include "Arduino.h"
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2009-06-01 10:32:11 +02:00
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#include "wiring_private.h"
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2010-10-17 19:36:02 +02:00
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// this next line disables the entire HardwareSerial.cpp,
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// this is so I can support Attiny series and any other chip without a uart
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#if defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H) || defined(UBRR2H) || defined(UBRR3H)
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2009-06-01 10:32:11 +02:00
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#include "HardwareSerial.h"
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2012-11-29 19:48:01 +01:00
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/*
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* on ATmega8, the uart and its bits are not numbered, so there is no "TXC0"
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2012-11-29 19:55:59 +01:00
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* definition.
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2012-11-29 19:48:01 +01:00
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*/
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#if !defined(TXC0)
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#if defined(TXC)
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#define TXC0 TXC
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#elif defined(TXC1)
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// Some devices have uart1 but no uart0
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#define TXC0 TXC1
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#else
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#error TXC0 not definable in HardwareSerial.h
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#endif
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#endif
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2009-06-01 10:32:11 +02:00
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// Define constants and variables for buffering incoming serial data. We're
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2011-03-05 20:17:26 +01:00
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// using a ring buffer (I think), in which head is the index of the location
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// to which to write the next incoming character and tail is the index of the
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// location from which to read.
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2010-10-17 19:36:02 +02:00
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#if (RAMEND < 1000)
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2011-03-05 20:17:26 +01:00
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#define SERIAL_BUFFER_SIZE 16
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2010-10-17 19:36:02 +02:00
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#else
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2011-03-05 20:17:26 +01:00
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#define SERIAL_BUFFER_SIZE 64
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2010-10-17 19:36:02 +02:00
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#endif
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2009-06-01 10:32:11 +02:00
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2010-10-17 19:36:02 +02:00
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struct ring_buffer
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{
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2011-03-05 20:17:26 +01:00
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unsigned char buffer[SERIAL_BUFFER_SIZE];
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2012-02-03 23:24:29 +01:00
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volatile unsigned int head;
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volatile unsigned int tail;
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2009-06-01 10:32:11 +02:00
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};
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2011-08-11 20:08:38 +02:00
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#if defined(USBCON)
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ring_buffer rx_buffer = { { 0 }, 0, 0};
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ring_buffer tx_buffer = { { 0 }, 0, 0};
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#endif
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2010-10-17 19:36:02 +02:00
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#if defined(UBRRH) || defined(UBRR0H)
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ring_buffer rx_buffer = { { 0 }, 0, 0 };
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2011-03-05 20:17:26 +01:00
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ring_buffer tx_buffer = { { 0 }, 0, 0 };
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2010-10-17 19:36:02 +02:00
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#endif
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#if defined(UBRR1H)
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ring_buffer rx_buffer1 = { { 0 }, 0, 0 };
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2011-03-05 20:17:26 +01:00
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ring_buffer tx_buffer1 = { { 0 }, 0, 0 };
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2010-10-17 19:36:02 +02:00
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#endif
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#if defined(UBRR2H)
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ring_buffer rx_buffer2 = { { 0 }, 0, 0 };
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2011-03-05 20:17:26 +01:00
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ring_buffer tx_buffer2 = { { 0 }, 0, 0 };
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2010-10-17 19:36:02 +02:00
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#endif
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#if defined(UBRR3H)
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ring_buffer rx_buffer3 = { { 0 }, 0, 0 };
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2011-03-05 20:17:26 +01:00
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ring_buffer tx_buffer3 = { { 0 }, 0, 0 };
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2009-06-01 10:32:11 +02:00
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#endif
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2011-03-05 20:17:26 +01:00
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inline void store_char(unsigned char c, ring_buffer *buffer)
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2009-06-01 10:32:11 +02:00
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{
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2011-03-05 20:17:26 +01:00
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int i = (unsigned int)(buffer->head + 1) % SERIAL_BUFFER_SIZE;
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2009-07-12 03:58:15 +02:00
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// if we should be storing the received character into the location
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// just before the tail (meaning that the head would advance to the
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// current location of the tail), we're about to overflow the buffer
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// and so we don't write the character or advance the head.
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2011-03-05 20:17:26 +01:00
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if (i != buffer->tail) {
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buffer->buffer[buffer->head] = c;
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buffer->head = i;
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2009-07-12 03:58:15 +02:00
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}
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2009-06-01 10:32:11 +02:00
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}
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2011-08-19 01:40:04 +02:00
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#if !defined(USART0_RX_vect) && defined(USART1_RX_vect)
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// do nothing - on the 32u4 the first USART is USART1
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2011-08-11 20:08:38 +02:00
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#else
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2013-03-29 15:17:54 +01:00
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#if !defined(USART_RX_vect) && !defined(USART0_RX_vect) && \
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!defined(USART_RXC_vect)
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2011-10-10 17:28:44 +02:00
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#error "Don't know what the Data Received vector is called for the first UART"
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2011-05-07 18:47:43 +02:00
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#else
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2011-05-07 19:04:13 +02:00
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void serialEvent() __attribute__((weak));
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void serialEvent() {}
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2011-08-31 21:52:56 +02:00
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#define serialEvent_implemented
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2010-10-17 19:36:02 +02:00
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#if defined(USART_RX_vect)
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2013-03-29 14:41:36 +01:00
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ISR(USART_RX_vect)
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2010-10-17 19:36:02 +02:00
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#elif defined(USART0_RX_vect)
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2013-03-29 14:41:36 +01:00
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ISR(USART0_RX_vect)
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2013-03-29 15:17:54 +01:00
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#elif defined(USART_RXC_vect)
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ISR(USART_RXC_vect) // ATmega8
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2011-05-07 18:47:43 +02:00
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#endif
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2010-10-17 19:36:02 +02:00
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{
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#if defined(UDR0)
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2012-08-12 16:57:57 +02:00
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if (bit_is_clear(UCSR0A, UPE0)) {
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unsigned char c = UDR0;
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store_char(c, &rx_buffer);
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} else {
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unsigned char c = UDR0;
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};
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2010-10-17 19:36:02 +02:00
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#elif defined(UDR)
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2012-08-12 17:35:48 +02:00
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if (bit_is_clear(UCSRA, PE)) {
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2012-08-12 16:57:57 +02:00
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unsigned char c = UDR;
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store_char(c, &rx_buffer);
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} else {
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unsigned char c = UDR;
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};
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2010-10-17 19:36:02 +02:00
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#else
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#error UDR not defined
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#endif
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}
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#endif
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2011-08-19 01:40:04 +02:00
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#endif
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2009-06-01 10:32:11 +02:00
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2010-10-17 19:36:02 +02:00
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#if defined(USART1_RX_vect)
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2011-05-07 19:04:13 +02:00
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void serialEvent1() __attribute__((weak));
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void serialEvent1() {}
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2011-08-31 21:52:56 +02:00
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#define serialEvent1_implemented
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2013-03-29 14:41:36 +01:00
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ISR(USART1_RX_vect)
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2010-10-17 19:36:02 +02:00
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{
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2012-08-12 16:57:57 +02:00
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if (bit_is_clear(UCSR1A, UPE1)) {
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unsigned char c = UDR1;
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store_char(c, &rx_buffer1);
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} else {
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unsigned char c = UDR1;
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};
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2010-10-17 19:36:02 +02:00
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}
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2009-06-01 10:32:11 +02:00
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#endif
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2010-10-17 19:36:02 +02:00
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#if defined(USART2_RX_vect) && defined(UDR2)
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2011-05-07 19:04:13 +02:00
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void serialEvent2() __attribute__((weak));
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void serialEvent2() {}
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2011-08-31 21:52:56 +02:00
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#define serialEvent2_implemented
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2013-03-29 14:41:36 +01:00
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ISR(USART2_RX_vect)
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2010-10-17 19:36:02 +02:00
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{
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2012-08-12 16:57:57 +02:00
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if (bit_is_clear(UCSR2A, UPE2)) {
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unsigned char c = UDR2;
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store_char(c, &rx_buffer2);
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} else {
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unsigned char c = UDR2;
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};
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2010-10-17 19:36:02 +02:00
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}
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2009-06-01 10:32:11 +02:00
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#endif
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2010-10-17 19:36:02 +02:00
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#if defined(USART3_RX_vect) && defined(UDR3)
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2011-05-07 19:04:13 +02:00
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void serialEvent3() __attribute__((weak));
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void serialEvent3() {}
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2011-08-31 21:52:56 +02:00
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#define serialEvent3_implemented
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2013-03-29 14:41:36 +01:00
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ISR(USART3_RX_vect)
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2010-10-17 19:36:02 +02:00
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{
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2012-08-12 16:57:57 +02:00
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if (bit_is_clear(UCSR3A, UPE3)) {
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unsigned char c = UDR3;
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store_char(c, &rx_buffer3);
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} else {
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unsigned char c = UDR3;
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};
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2010-10-17 19:36:02 +02:00
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}
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2009-06-01 10:32:11 +02:00
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#endif
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2011-08-31 21:52:56 +02:00
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void serialEventRun(void)
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{
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#ifdef serialEvent_implemented
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2011-09-07 23:47:17 +02:00
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if (Serial.available()) serialEvent();
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2011-08-31 21:52:56 +02:00
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#endif
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#ifdef serialEvent1_implemented
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2011-09-07 23:47:17 +02:00
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if (Serial1.available()) serialEvent1();
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2011-08-31 21:52:56 +02:00
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#endif
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#ifdef serialEvent2_implemented
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2011-09-07 23:47:17 +02:00
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if (Serial2.available()) serialEvent2();
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2011-08-31 21:52:56 +02:00
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#endif
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#ifdef serialEvent3_implemented
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2011-09-07 23:47:17 +02:00
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if (Serial3.available()) serialEvent3();
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2011-08-31 21:52:56 +02:00
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#endif
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}
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2010-10-17 19:36:02 +02:00
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2011-09-05 19:08:05 +02:00
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#if !defined(USART0_UDRE_vect) && defined(USART1_UDRE_vect)
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// do nothing - on the 32u4 the first USART is USART1
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#else
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2011-03-05 20:17:26 +01:00
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#if !defined(UART0_UDRE_vect) && !defined(UART_UDRE_vect) && !defined(USART0_UDRE_vect) && !defined(USART_UDRE_vect)
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2011-10-10 17:28:44 +02:00
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#error "Don't know what the Data Register Empty vector is called for the first UART"
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2011-03-05 20:17:26 +01:00
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#else
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#if defined(UART0_UDRE_vect)
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ISR(UART0_UDRE_vect)
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#elif defined(UART_UDRE_vect)
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ISR(UART_UDRE_vect)
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#elif defined(USART0_UDRE_vect)
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ISR(USART0_UDRE_vect)
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#elif defined(USART_UDRE_vect)
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ISR(USART_UDRE_vect)
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#endif
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{
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if (tx_buffer.head == tx_buffer.tail) {
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// Buffer empty, so disable interrupts
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#if defined(UCSR0B)
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cbi(UCSR0B, UDRIE0);
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#else
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cbi(UCSRB, UDRIE);
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#endif
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}
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else {
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// There is more data in the output buffer. Send the next byte
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unsigned char c = tx_buffer.buffer[tx_buffer.tail];
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tx_buffer.tail = (tx_buffer.tail + 1) % SERIAL_BUFFER_SIZE;
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#if defined(UDR0)
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UDR0 = c;
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#elif defined(UDR)
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UDR = c;
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#else
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#error UDR not defined
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#endif
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}
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}
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#endif
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2011-08-19 01:40:04 +02:00
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#endif
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2011-03-05 20:17:26 +01:00
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#ifdef USART1_UDRE_vect
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ISR(USART1_UDRE_vect)
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{
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if (tx_buffer1.head == tx_buffer1.tail) {
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// Buffer empty, so disable interrupts
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cbi(UCSR1B, UDRIE1);
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}
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else {
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// There is more data in the output buffer. Send the next byte
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unsigned char c = tx_buffer1.buffer[tx_buffer1.tail];
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tx_buffer1.tail = (tx_buffer1.tail + 1) % SERIAL_BUFFER_SIZE;
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UDR1 = c;
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}
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}
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#endif
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#ifdef USART2_UDRE_vect
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ISR(USART2_UDRE_vect)
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{
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if (tx_buffer2.head == tx_buffer2.tail) {
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// Buffer empty, so disable interrupts
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cbi(UCSR2B, UDRIE2);
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}
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else {
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// There is more data in the output buffer. Send the next byte
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unsigned char c = tx_buffer2.buffer[tx_buffer2.tail];
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tx_buffer2.tail = (tx_buffer2.tail + 1) % SERIAL_BUFFER_SIZE;
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UDR2 = c;
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}
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}
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#endif
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#ifdef USART3_UDRE_vect
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ISR(USART3_UDRE_vect)
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{
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if (tx_buffer3.head == tx_buffer3.tail) {
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// Buffer empty, so disable interrupts
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cbi(UCSR3B, UDRIE3);
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}
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else {
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// There is more data in the output buffer. Send the next byte
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unsigned char c = tx_buffer3.buffer[tx_buffer3.tail];
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tx_buffer3.tail = (tx_buffer3.tail + 1) % SERIAL_BUFFER_SIZE;
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UDR3 = c;
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}
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}
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#endif
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2010-10-17 19:36:02 +02:00
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2009-06-01 10:32:11 +02:00
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// Constructors ////////////////////////////////////////////////////////////////
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2011-03-05 20:17:26 +01:00
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HardwareSerial::HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer,
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2009-06-01 10:32:11 +02:00
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volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
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volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
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2012-08-12 16:57:57 +02:00
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volatile uint8_t *ucsrc, volatile uint8_t *udr,
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2011-03-05 20:17:26 +01:00
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uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x)
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2009-06-01 10:32:11 +02:00
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{
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_rx_buffer = rx_buffer;
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2011-03-05 20:17:26 +01:00
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_tx_buffer = tx_buffer;
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2009-06-01 10:32:11 +02:00
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_ubrrh = ubrrh;
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_ubrrl = ubrrl;
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_ucsra = ucsra;
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_ucsrb = ucsrb;
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2012-08-12 16:57:57 +02:00
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_ucsrc = ucsrc;
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2009-06-01 10:32:11 +02:00
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_udr = udr;
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_rxen = rxen;
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_txen = txen;
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_rxcie = rxcie;
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2011-03-05 20:17:26 +01:00
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_udrie = udrie;
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2009-07-12 03:58:15 +02:00
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_u2x = u2x;
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2009-06-01 10:32:11 +02:00
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}
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// Public Methods //////////////////////////////////////////////////////////////
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2011-05-12 22:58:56 +02:00
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void HardwareSerial::begin(unsigned long baud)
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2009-06-01 10:32:11 +02:00
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{
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2009-07-12 04:58:59 +02:00
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uint16_t baud_setting;
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2010-11-12 05:28:21 +01:00
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bool use_u2x = true;
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#if F_CPU == 16000000UL
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// hardcoded exception for compatibility with the bootloader shipped
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// with the Duemilanove and previous boards and the firmware on the 8U2
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// on the Uno and Mega 2560.
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if (baud == 57600) {
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use_u2x = false;
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2009-07-12 04:58:59 +02:00
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}
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2010-11-12 05:28:21 +01:00
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#endif
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2011-05-14 18:25:39 +02:00
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try_again:
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2009-07-12 04:58:59 +02:00
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if (use_u2x) {
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*_ucsra = 1 << _u2x;
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baud_setting = (F_CPU / 4 / baud - 1) / 2;
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} else {
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*_ucsra = 0;
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baud_setting = (F_CPU / 8 / baud - 1) / 2;
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}
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2011-05-14 18:25:39 +02:00
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if ((baud_setting > 4095) && use_u2x)
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{
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use_u2x = false;
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goto try_again;
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}
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2009-07-12 04:58:59 +02:00
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// assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
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*_ubrrh = baud_setting >> 8;
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*_ubrrl = baud_setting;
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2012-08-28 14:02:54 +02:00
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transmitting = false;
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2009-06-01 10:32:11 +02:00
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sbi(*_ucsrb, _rxen);
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sbi(*_ucsrb, _txen);
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sbi(*_ucsrb, _rxcie);
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2011-03-06 18:20:42 +01:00
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cbi(*_ucsrb, _udrie);
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2009-06-01 10:32:11 +02:00
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}
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2012-08-14 15:50:36 +02:00
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void HardwareSerial::begin(unsigned long baud, byte config)
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2012-08-12 16:57:57 +02:00
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{
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uint16_t baud_setting;
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2012-08-14 15:50:36 +02:00
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uint8_t current_config;
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2012-08-12 16:57:57 +02:00
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bool use_u2x = true;
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#if F_CPU == 16000000UL
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// hardcoded exception for compatibility with the bootloader shipped
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// with the Duemilanove and previous boards and the firmware on the 8U2
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// on the Uno and Mega 2560.
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if (baud == 57600) {
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use_u2x = false;
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}
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#endif
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try_again:
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if (use_u2x) {
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*_ucsra = 1 << _u2x;
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baud_setting = (F_CPU / 4 / baud - 1) / 2;
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} else {
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*_ucsra = 0;
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baud_setting = (F_CPU / 8 / baud - 1) / 2;
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}
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if ((baud_setting > 4095) && use_u2x)
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{
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use_u2x = false;
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goto try_again;
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}
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// assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
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*_ubrrh = baud_setting >> 8;
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*_ubrrl = baud_setting;
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2012-08-30 14:47:35 +02:00
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//set the data bits, parity, and stop bits
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#if defined(__AVR_ATmega8__)
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config |= 0x80; // select UCSRC register (shared with UBRRH)
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#endif
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*_ucsrc = config;
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2012-08-12 16:57:57 +02:00
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sbi(*_ucsrb, _rxen);
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sbi(*_ucsrb, _txen);
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sbi(*_ucsrb, _rxcie);
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cbi(*_ucsrb, _udrie);
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}
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2009-12-23 01:00:17 +01:00
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void HardwareSerial::end()
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{
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2011-03-06 18:20:42 +01:00
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// wait for transmission of outgoing data
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while (_tx_buffer->head != _tx_buffer->tail)
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;
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2009-12-23 01:00:17 +01:00
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cbi(*_ucsrb, _rxen);
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cbi(*_ucsrb, _txen);
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cbi(*_ucsrb, _rxcie);
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2011-03-05 20:17:26 +01:00
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cbi(*_ucsrb, _udrie);
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2011-03-06 18:20:42 +01:00
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// clear any received data
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_rx_buffer->head = _rx_buffer->tail;
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2009-12-23 01:00:17 +01:00
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}
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2010-08-03 00:23:48 +02:00
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int HardwareSerial::available(void)
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2009-06-01 10:32:11 +02:00
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{
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2011-03-05 20:17:26 +01:00
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return (unsigned int)(SERIAL_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % SERIAL_BUFFER_SIZE;
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2009-06-01 10:32:11 +02:00
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}
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2010-07-05 01:31:55 +02:00
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int HardwareSerial::peek(void)
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{
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if (_rx_buffer->head == _rx_buffer->tail) {
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return -1;
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} else {
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return _rx_buffer->buffer[_rx_buffer->tail];
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}
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}
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2009-06-01 10:32:11 +02:00
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int HardwareSerial::read(void)
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{
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2009-07-12 03:58:15 +02:00
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// if the head isn't ahead of the tail, we don't have any characters
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if (_rx_buffer->head == _rx_buffer->tail) {
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return -1;
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} else {
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unsigned char c = _rx_buffer->buffer[_rx_buffer->tail];
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2011-03-05 20:17:26 +01:00
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_rx_buffer->tail = (unsigned int)(_rx_buffer->tail + 1) % SERIAL_BUFFER_SIZE;
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2009-07-12 03:58:15 +02:00
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return c;
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}
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2009-06-01 10:32:11 +02:00
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}
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void HardwareSerial::flush()
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{
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2012-08-28 14:02:54 +02:00
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// UDR is kept full while the buffer is not empty, so TXC triggers when EMPTY && SENT
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while (transmitting && ! (*_ucsra & _BV(TXC0)));
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transmitting = false;
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2009-06-01 10:32:11 +02:00
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}
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2011-08-26 22:08:14 +02:00
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size_t HardwareSerial::write(uint8_t c)
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2009-06-01 10:32:11 +02:00
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{
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2011-03-05 20:17:26 +01:00
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int i = (_tx_buffer->head + 1) % SERIAL_BUFFER_SIZE;
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// If the output buffer is full, there's nothing for it other than to
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// wait for the interrupt handler to empty it a bit
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2011-08-24 01:12:03 +02:00
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// ???: return 0 here instead?
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2011-03-05 20:17:26 +01:00
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while (i == _tx_buffer->tail)
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2009-07-12 03:58:15 +02:00
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;
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2011-03-05 20:17:26 +01:00
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_tx_buffer->buffer[_tx_buffer->head] = c;
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_tx_buffer->head = i;
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2011-03-06 17:47:18 +01:00
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sbi(*_ucsrb, _udrie);
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2012-08-28 14:02:54 +02:00
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// clear the TXC bit -- "can be cleared by writing a one to its bit location"
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transmitting = true;
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sbi(*_ucsra, TXC0);
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2011-08-24 01:12:03 +02:00
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return 1;
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2009-06-01 10:32:11 +02:00
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}
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2012-04-01 18:54:35 +02:00
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HardwareSerial::operator bool() {
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return true;
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}
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2009-06-01 10:32:11 +02:00
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// Preinstantiate Objects //////////////////////////////////////////////////////
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2010-10-17 19:36:02 +02:00
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#if defined(UBRRH) && defined(UBRRL)
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2012-08-12 16:57:57 +02:00
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HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UCSRC, &UDR, RXEN, TXEN, RXCIE, UDRIE, U2X);
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2010-10-17 19:36:02 +02:00
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#elif defined(UBRR0H) && defined(UBRR0L)
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2012-08-12 16:57:57 +02:00
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HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UCSR0C, &UDR0, RXEN0, TXEN0, RXCIE0, UDRIE0, U2X0);
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2010-10-17 19:36:02 +02:00
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#elif defined(USBCON)
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2011-08-19 01:40:04 +02:00
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// do nothing - Serial object and buffers are initialized in CDC code
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2009-06-01 10:32:11 +02:00
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#else
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2010-10-17 19:36:02 +02:00
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#error no serial port defined (port 0)
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2009-06-01 10:32:11 +02:00
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#endif
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2010-10-17 19:36:02 +02:00
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#if defined(UBRR1H)
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2012-08-12 16:57:57 +02:00
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HardwareSerial Serial1(&rx_buffer1, &tx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UCSR1C, &UDR1, RXEN1, TXEN1, RXCIE1, UDRIE1, U2X1);
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2010-10-17 19:36:02 +02:00
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#endif
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#if defined(UBRR2H)
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2012-08-12 16:57:57 +02:00
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HardwareSerial Serial2(&rx_buffer2, &tx_buffer2, &UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UCSR2C, &UDR2, RXEN2, TXEN2, RXCIE2, UDRIE2, U2X2);
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2010-10-17 19:36:02 +02:00
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#endif
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#if defined(UBRR3H)
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2012-08-12 16:57:57 +02:00
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HardwareSerial Serial3(&rx_buffer3, &tx_buffer3, &UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UCSR3C, &UDR3, RXEN3, TXEN3, RXCIE3, UDRIE3, U2X3);
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2009-06-01 10:32:11 +02:00
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#endif
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2010-10-17 19:36:02 +02:00
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#endif // whole file
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