mirror of
https://github.com/arduino/Arduino.git
synced 2025-03-13 10:29:35 +01:00
[sam] added support for DACC in analogWrite
(cherry-pick from Thibault Richard commit a1d6cb43a5097414e8933e8d75d8690ee3311f94)
This commit is contained in:
Cristian Maglie
parent
9113c454f4
commit
221c10842e
Binary file not shown.
@ -1,418 +0,0 @@
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adc.o:
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00000000 T adc_configure_power_save
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00000000 T adc_configure_sequence
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00000000 T adc_configure_timing
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00000000 T adc_configure_trigger
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||||
00000000 T adc_disable_all_channel
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||||
00000000 T adc_disable_anch
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00000000 T adc_disable_channel
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||||
00000000 T adc_disable_channel_differential_input
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||||
00000000 T adc_disable_channel_input_offset
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||||
00000000 T adc_disable_interrupt
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00000000 T adc_disable_tag
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00000000 T adc_disable_ts
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||||
00000000 T adc_enable_all_channel
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||||
00000000 T adc_enable_anch
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00000000 T adc_enable_channel
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00000000 T adc_enable_channel_differential_input
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||||
00000000 T adc_enable_channel_input_offset
|
||||
00000000 T adc_enable_interrupt
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||||
00000000 T adc_enable_tag
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||||
00000000 T adc_enable_ts
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||||
00000000 T adc_get_actual_adc_clock
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||||
00000000 T adc_get_channel_status
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||||
00000000 T adc_get_channel_value
|
||||
00000000 T adc_get_comparison_mode
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||||
00000000 T adc_get_interrupt_mask
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||||
00000000 T adc_get_latest_value
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||||
00000000 T adc_get_overrun_status
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00000000 T adc_get_pdc_base
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00000000 T adc_get_status
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00000000 T adc_get_tag
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00000000 T adc_get_writeprotect_status
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00000000 T adc_init
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00000000 T adc_set_bias_current
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00000000 T adc_set_channel_input_gain
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00000000 T adc_set_comparison_channel
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00000000 T adc_set_comparison_mode
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00000000 T adc_set_comparison_window
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00000000 T adc_set_resolution
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00000000 T adc_set_writeprotect
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00000000 T adc_start
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00000000 T adc_start_sequencer
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00000000 T adc_stop
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00000000 T adc_stop_sequencer
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adc12_sam3u.o:
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interrupt_sam_nvic.o:
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00000000 D g_interrupt_enabled
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pio.o:
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00000000 T PIO_Clear
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00000000 T PIO_Configure
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00000000 T PIO_DisableInterrupt
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00000000 T PIO_Get
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00000000 T PIO_GetOutputDataStatus
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00000000 T PIO_PullUp
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00000000 T PIO_Set
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00000000 T PIO_SetDebounceFilter
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00000000 T PIO_SetInput
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00000000 T PIO_SetOutput
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00000000 T PIO_SetPeripheral
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pmc.o:
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00000000 T pmc_clr_fast_startup_input
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00000000 T pmc_disable_all_pck
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00000000 T pmc_disable_all_periph_clk
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00000000 T pmc_disable_interrupt
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00000000 T pmc_disable_pck
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00000000 T pmc_disable_periph_clk
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00000000 T pmc_disable_pllack
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00000000 T pmc_disable_udpck
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00000000 T pmc_disable_upll_clock
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00000000 T pmc_enable_all_pck
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00000000 T pmc_enable_all_periph_clk
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00000000 T pmc_enable_backupmode
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00000000 T pmc_enable_interrupt
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00000000 T pmc_enable_pck
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00000000 T pmc_enable_periph_clk
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00000000 T pmc_enable_pllack
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00000000 T pmc_enable_sleepmode
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00000000 T pmc_enable_udpck
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00000000 T pmc_enable_upll_clock
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00000000 T pmc_enable_waitmode
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00000000 T pmc_get_interrupt_mask
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00000000 T pmc_get_status
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00000000 T pmc_get_writeprotect_status
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00000000 T pmc_is_locked_pllack
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00000000 T pmc_is_locked_upll
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00000000 T pmc_is_pck_enabled
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00000000 T pmc_is_periph_clk_enabled
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00000000 T pmc_mck_set_prescaler
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00000000 T pmc_mck_set_source
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00000000 T pmc_osc_disable_fastrc
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00000000 T pmc_osc_disable_xtal
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00000000 T pmc_osc_enable_fastrc
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00000000 T pmc_osc_is_ready_32kxtal
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00000000 T pmc_osc_is_ready_mainck
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00000000 T pmc_pck_set_prescaler
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00000000 T pmc_pck_set_source
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00000000 T pmc_set_fast_startup_input
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00000000 T pmc_set_writeprotect
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00000000 T pmc_switch_mainck_to_fastrc
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00000000 T pmc_switch_mainck_to_xtal
|
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00000000 T pmc_switch_mck_to_mainck
|
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00000000 T pmc_switch_mck_to_pllack
|
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00000000 T pmc_switch_mck_to_sclk
|
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00000000 T pmc_switch_mck_to_upllck
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00000000 T pmc_switch_pck_to_mainck
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00000000 T pmc_switch_pck_to_pllack
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00000000 T pmc_switch_pck_to_sclk
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00000000 T pmc_switch_pck_to_upllck
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00000000 T pmc_switch_sclk_to_32kxtal
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00000000 T pmc_switch_udpck_to_pllack
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00000000 T pmc_switch_udpck_to_upllck
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pwmc.o:
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00000024 r .LC0
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00000000 r .LC1
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0000016c r .LC10
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0000019c r .LC11
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000001cc r .LC12
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000001fc r .LC13
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00000204 r .LC14
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00000014 r .LC2
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00000050 r .LC3
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0000007c r .LC4
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000000a8 r .LC5
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000000dc r .LC6
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00000108 r .LC7
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00000134 r .LC8
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00000160 r .LC9
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00000000 t FindClockConfiguration
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00000000 T PWMC_ConfigureChannel
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00000000 T PWMC_ConfigureChannelExt
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00000000 T PWMC_ConfigureClocks
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00000000 T PWMC_ConfigureComparisonUnit
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00000000 T PWMC_ConfigureEventLineMode
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00000000 T PWMC_ConfigureSyncChannel
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00000000 T PWMC_DisableChannel
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00000000 T PWMC_DisableChannelIt
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00000000 T PWMC_DisableIt
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00000000 T PWMC_DisableOverrideOutput
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00000000 T PWMC_EnableChannel
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00000000 T PWMC_EnableChannelIt
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00000000 T PWMC_EnableFaultProtection
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00000000 T PWMC_EnableIt
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00000000 T PWMC_EnableOverrideOutput
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00000000 T PWMC_FaultClear
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00000000 T PWMC_SetDeadTime
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00000000 T PWMC_SetDutyCycle
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00000000 T PWMC_SetFaultMode
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00000000 T PWMC_SetFaultProtectionValue
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00000000 T PWMC_SetOverrideValue
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00000000 T PWMC_SetPeriod
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00000000 T PWMC_SetSyncChannelUpdatePeriod
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00000000 T PWMC_SetSyncChannelUpdateUnlock
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00000000 T PWMC_WriteBuffer
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U __assert_func
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00000000 r __func__.3192
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00000000 r __func__.3203
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00000000 r __func__.3218
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00000000 r __func__.3229
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00000000 r __func__.3240
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00000000 r __func__.3247
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00000000 r __func__.3331
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00000000 r __func__.3337
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rtc.o:
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00000000 r .LC0
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00000010 r .LC1
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0000002c r .LC2
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00000000 T RTC_ClearSCCR
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00000000 T RTC_DisableIt
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00000000 T RTC_EnableIt
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00000000 T RTC_GetDate
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00000000 T RTC_GetHourMode
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00000000 T RTC_GetSR
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00000000 T RTC_GetTime
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00000000 T RTC_SetDate
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00000000 T RTC_SetDateAlarm
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00000000 T RTC_SetHourMode
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00000000 T RTC_SetTime
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00000000 T RTC_SetTimeAlarm
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U __assert_func
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00000000 r __func__.3189
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00000000 r __func__.3198
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00000000 r __func__.3203
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rtt.o:
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00000000 r .LC0
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00000010 r .LC1
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0000002c r .LC2
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00000000 T RTT_EnableIT
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00000000 T RTT_GetStatus
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00000000 T RTT_GetTime
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00000000 T RTT_SetAlarm
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00000000 T RTT_SetPrescaler
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U __assert_func
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00000000 r __func__.3196
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00000000 r __func__.3204
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spi.o:
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00000000 T SPI_Configure
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00000000 T SPI_ConfigureNPCS
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00000000 T SPI_Disable
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00000000 T SPI_DisableIt
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||||
00000000 T SPI_Enable
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00000000 T SPI_EnableIt
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00000000 T SPI_GetStatus
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00000000 T SPI_IsFinished
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00000000 T SPI_Read
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00000000 T SPI_Write
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U pmc_enable_periph_clk
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tc.o:
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00000000 r .LC0
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00000010 r .LC1
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00000000 T TC_Configure
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00000000 T TC_FindMckDivisor
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00000000 T TC_Start
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00000000 T TC_Stop
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U __assert_func
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00000000 r __func__.3191
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00000000 r __func__.3197
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00000000 r __func__.3203
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timetick.o:
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00000000 T GetTickCount
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00000000 t NVIC_SetPriority
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00000000 T Sleep
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00000000 t SysTick_Config
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00000000 T TimeTick_Configure
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00000000 T TimeTick_Increment
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00000000 T Wait
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00000000 b _dwTickCount
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twi.o:
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00000000 r .LC0
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00000010 r .LC1
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00000018 r .LC2
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00000024 r .LC3
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00000054 r .LC4
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00000064 r .LC5
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0000007c r .LC6
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0000009c r .LC7
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000000a8 r .LC8
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00000000 T TWI_ByteReceived
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00000000 T TWI_ByteSent
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00000000 T TWI_ConfigureMaster
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00000000 T TWI_ConfigureSlave
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00000000 T TWI_DisableIt
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00000000 T TWI_EnableIt
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00000000 T TWI_GetMaskedStatus
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00000000 T TWI_GetStatus
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00000000 T TWI_ReadByte
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00000000 T TWI_SendSTOPCondition
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00000000 T TWI_StartRead
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00000000 T TWI_StartWrite
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00000000 T TWI_Stop
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00000000 T TWI_TransferComplete
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00000000 T TWI_WriteByte
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U __assert_func
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00000000 r __func__.3556
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00000000 r __func__.3571
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00000000 r __func__.3575
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00000000 r __func__.3582
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00000000 r __func__.3586
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00000000 r __func__.3591
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00000000 r __func__.3599
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00000000 r __func__.3613
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00000000 r __func__.3618
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00000000 r __func__.3622
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00000000 r __func__.3627
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00000000 r __func__.3631
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udp.o:
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udphs.o:
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uotghs.o:
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00000000 t NVIC_EnableIRQ
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00000000 t NVIC_SetPriority
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00000000 T UDD_Attach
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00000000 T UDD_ClearIN
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00000000 T UDD_ClearOUT
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00000000 T UDD_ClearSetupInt
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00000000 T UDD_Detach
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00000000 T UDD_FifoByteCount
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00000000 T UDD_GetFrameNumber
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00000000 T UDD_Init
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00000000 T UDD_InitEP
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00000000 T UDD_InitEndpoints
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00000000 T UDD_ReadWriteAllowed
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00000000 T UDD_ReceivedSetupInt
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00000000 T UDD_Recv
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00000000 T UDD_Recv8
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00000000 T UDD_ReleaseRX
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00000000 T UDD_ReleaseTX
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00000000 T UDD_Send
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00000000 T UDD_Send8
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00000000 T UDD_SetAddress
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00000000 T UDD_SetStack
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00000000 T UDD_Stall
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00000000 T UDD_WaitForINOrOUT
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00000000 T UDD_WaitIN
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00000000 T UDD_WaitOUT
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00000000 T UOTGHS_Handler
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00000000 t cpu_irq_is_enabled_flags
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00000000 t cpu_irq_restore
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00000000 t cpu_irq_save
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U g_interrupt_enabled
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00000000 b gpf_isr
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U pmc_enable_periph_clk
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U pmc_enable_udpck
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U pmc_enable_upll_clock
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U pmc_switch_udpck_to_upllck
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00000000 b ul_recv_fifo_ptr
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00000000 b ul_send_fifo_ptr
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usart.o:
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00000000 r .LC0
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00000014 r .LC1
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00000000 T USART_Configure
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00000000 T USART_DisableIt
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00000000 T USART_EnableIt
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00000000 T USART_GetChar
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00000000 T USART_GetStatus
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00000000 T USART_IsDataAvailable
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00000000 T USART_IsRxReady
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00000000 T USART_PutChar
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00000000 T USART_Read
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00000000 T USART_ReadBuffer
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00000000 T USART_SetIrdaFilter
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00000000 T USART_SetReceiverEnabled
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00000000 T USART_SetTransmitterEnabled
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00000000 T USART_Write
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00000000 T USART_WriteBuffer
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U __assert_func
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00000000 r __func__.3477
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wdt.o:
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00000000 T WDT_Disable
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00000000 T WDT_Enable
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00000000 T WDT_GetPeriod
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00000000 T WDT_GetStatus
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00000000 T WDT_Restart
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system_sam3xa.o:
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00000000 D SystemCoreClock
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00000000 T SystemCoreClockUpdate
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00000000 T SystemInit
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00000000 T system_init_flash
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startup_sam3xa.o:
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00000000 W ADC_Handler
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00000000 W BusFault_Handler
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00000000 W CAN0_Handler
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00000000 W CAN1_Handler
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00000000 W DACC_Handler
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00000000 W DMAC_Handler
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00000000 W DebugMon_Handler
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00000000 T Dummy_Handler
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00000000 W EFC0_Handler
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00000000 W EFC1_Handler
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00000000 W EMAC_Handler
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00000000 W HSMCI_Handler
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00000000 W HardFault_Handler
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00000000 W MemManage_Handler
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00000000 W NMI_Handler
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00000000 W PIOA_Handler
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00000000 W PIOB_Handler
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00000000 W PIOC_Handler
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00000000 W PIOD_Handler
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00000000 W PMC_Handler
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00000000 W PWM_Handler
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00000000 W PendSV_Handler
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00000000 W RSTC_Handler
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00000000 W RTC_Handler
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00000000 W RTT_Handler
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00000000 T Reset_Handler
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00000000 W SMC_Handler
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00000000 W SPI0_Handler
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00000000 W SSC_Handler
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00000000 W SUPC_Handler
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00000000 W SVC_Handler
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00000000 W SysTick_Handler
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00000000 W TC0_Handler
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00000000 W TC1_Handler
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00000000 W TC2_Handler
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00000000 W TC3_Handler
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00000000 W TC4_Handler
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00000000 W TC5_Handler
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00000000 W TC6_Handler
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00000000 W TC7_Handler
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00000000 W TC8_Handler
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00000000 W TRNG_Handler
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00000000 W TWI0_Handler
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00000000 W TWI1_Handler
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00000000 W UART_Handler
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00000000 W UOTGHS_Handler
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00000000 W USART0_Handler
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00000000 W USART1_Handler
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00000000 W USART2_Handler
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00000000 W USART3_Handler
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00000000 W UsageFault_Handler
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00000000 W WDT_Handler
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U __libc_init_array
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U _erelocate
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||||
U _estack
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||||
U _etext
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U _ezero
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||||
U _sfixed
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U _srelocate
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U _szero
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00000000 R exception_table
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U main
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@ -193,6 +193,50 @@ void analogOutputInit(void) {
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void analogWrite(uint32_t ulPin, uint32_t ulValue) {
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uint32_t attr = g_APinDescription[ulPin].ulPinAttribute;
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if ((attr & PIN_ATTR_ANALOG) == PIN_ATTR_ANALOG) {
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EAnalogChannel channel = g_APinDescription[ulPin].ulADCChannelNumber;
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if (channel == DAC0 || channel == DAC1) {
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uint32_t chDACC = ((channel == DAC0) ? 0 : 1);
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if ((dacc_get_channel_status(DACC_INTERFACE) & (1 << chDACC)) == 0) {
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/* Enable clock for DACC_INTERFACE */
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pmc_enable_periph_clk(DACC_INTERFACE_ID);
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/* Reset DACC registers */
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dacc_reset(DACC_INTERFACE);
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/* Half word transfer mode */
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dacc_set_transfer_mode(DACC_INTERFACE, 0);
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/* Power save:
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* sleep mode - 0 (disabled)
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* fast wakeup - 0 (disabled)
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*/
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dacc_set_power_save(DACC_INTERFACE, 0, 0);
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/* Timing:
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* refresh - 0x08 (1024*8 dacc clocks)
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* max speed mode - 0 (disabled)
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* startup time - 0x10 (1024 dacc clocks)
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*/
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dacc_set_timing(DACC_INTERFACE, 0x08, 0, 0x10);
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/* Disable TAG and select output channel chDACC */
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dacc_set_channel_selection(DACC_INTERFACE, chDACC);
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/* Enable output channel chDACC */
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dacc_enable_channel(DACC_INTERFACE, chDACC);
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/* Set up analog current */
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dacc_set_analog_control(DACC_INTERFACE, DACC_ACR_IBCTLCH0(0x02) |
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DACC_ACR_IBCTLCH1(0x02) |
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DACC_ACR_IBCTLDACCORE(0x01));
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}
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// Write user value
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dacc_write_conversion_data(DACC_INTERFACE, ulValue);
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return;
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}
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}
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if ((attr & PIN_ATTR_PWM) == PIN_ATTR_PWM) {
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if (!PWMEnabled) {
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// PWM Startup code
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@ -42,6 +42,7 @@
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* Peripherals
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*/
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#include "include/adc.h"
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#include "include/dacc.h"
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#include "include/interrupt_sam_nvic.h"
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#include "include/pio.h"
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#include "include/pmc.h"
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102
hardware/arduino/sam/system/libsam/include/dacc.h
Normal file
102
hardware/arduino/sam/system/libsam/include/dacc.h
Normal file
@ -0,0 +1,102 @@
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2011-2012, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following condition is met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef DACC_H_INCLUDED
|
||||
#define DACC_H_INCLUDED
|
||||
|
||||
#include "../chip.h"
|
||||
|
||||
/// @cond 0
|
||||
/**INDENT-OFF**/
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**INDENT-ON**/
|
||||
/// @endcond
|
||||
|
||||
//! DACC return codes
|
||||
typedef enum dacc_rc {
|
||||
DACC_RC_OK = 0, //!< Operation OK
|
||||
DACC_RC_INVALID_PARAM //!< Invalid parameter
|
||||
} dacc_rc_t;
|
||||
|
||||
#if SAM3N_SERIES
|
||||
//! DACC resolution in number of data bits
|
||||
# define DACC_RESOLUTION 10
|
||||
#else
|
||||
//! DACC resolution in number of data bits
|
||||
# define DACC_RESOLUTION 12
|
||||
#endif
|
||||
//! DACC max data value
|
||||
#define DACC_MAX_DATA ((1 << DACC_RESOLUTION) - 1)
|
||||
|
||||
void dacc_reset(Dacc *p_dacc);
|
||||
uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger);
|
||||
void dacc_disable_trigger(Dacc *p_dacc);
|
||||
uint32_t dacc_set_transfer_mode(Dacc *p_dacc, uint32_t ul_mode);
|
||||
void dacc_enable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask);
|
||||
void dacc_disable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask);
|
||||
uint32_t dacc_get_interrupt_mask(Dacc *p_dacc);
|
||||
uint32_t dacc_get_interrupt_status(Dacc *p_dacc);
|
||||
void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data);
|
||||
void dacc_set_writeprotect(Dacc *p_dacc, uint32_t ul_enable);
|
||||
uint32_t dacc_get_writeprotect_status(Dacc *p_dacc);
|
||||
Pdc *dacc_get_pdc_base(Dacc *p_dacc);
|
||||
|
||||
#if (SAM3N_SERIES) || defined(__DOXYGEN__)
|
||||
void dacc_enable(Dacc *p_dacc);
|
||||
void dacc_disable(Dacc *p_dacc);
|
||||
uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_startup,
|
||||
uint32_t ul_clock_divider);
|
||||
#endif /* (SAM3N_SERIES) */
|
||||
|
||||
#if (SAM3S_SERIES) || (SAM3XA_SERIES) || (SAM4S_SERIES) || defined(__DOXYGEN__)
|
||||
uint32_t dacc_set_channel_selection(Dacc *p_dacc, uint32_t ul_channel);
|
||||
void dacc_enable_flexible_selection(Dacc *p_dacc);
|
||||
|
||||
uint32_t dacc_set_power_save(Dacc *p_dacc, uint32_t ul_sleep_mode,
|
||||
uint32_t ul_fast_wakeup_mode);
|
||||
uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_refresh, uint32_t ul_maxs,
|
||||
uint32_t ul_startup);
|
||||
uint32_t dacc_enable_channel(Dacc *p_dacc, uint32_t ul_channel);
|
||||
uint32_t dacc_disable_channel(Dacc *p_dacc, uint32_t ul_channel);
|
||||
uint32_t dacc_get_channel_status(Dacc *p_dacc);
|
||||
uint32_t dacc_set_analog_control(Dacc *p_dacc, uint32_t ul_analog_control);
|
||||
uint32_t dacc_get_analog_control(Dacc *p_dacc);
|
||||
#endif /* (SAM3S_SERIES) || (SAM3XA_SERIES) */
|
||||
|
||||
/// @cond 0
|
||||
/**INDENT-OFF**/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**INDENT-ON**/
|
||||
/// @endcond
|
||||
|
||||
#endif /* DACC_H_INCLUDED */
|
||||
481
hardware/arduino/sam/system/libsam/source/dacc.c
Normal file
481
hardware/arduino/sam/system/libsam/source/dacc.c
Normal file
@ -0,0 +1,481 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* SAM Software Package License
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2011-2012, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following condition is met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "dacc.h"
|
||||
|
||||
/// @cond 0
|
||||
/**INDENT-OFF**/
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**INDENT-ON**/
|
||||
/// @endcond
|
||||
|
||||
/**
|
||||
* \defgroup sam_drivers_dacc_group Digital-to-Analog Converter Controller (DACC)
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* Driver for the Digital-to-Analog Converter Controller. It provides access to the main
|
||||
* features of the DAC controller.
|
||||
*
|
||||
* \par Usage
|
||||
*
|
||||
* -# DACC clock should be enabled before using it.
|
||||
* - \ref pmc_enable_periph_clk() can be used to enable the clock.
|
||||
* -# Reset DACC with \ref dacc_reset().
|
||||
* -# If DACC can be enabled/disabled, uses \ref dacc_enable() and
|
||||
* \ref dacc_disable().
|
||||
* -# Initialize DACC timing with \ref dacc_set_timing() (different DAC
|
||||
* peripheral may require different parameters).
|
||||
* -# Write conversion data with \ref dacc_write_conversion_data().
|
||||
* -# Configure trigger with \ref dacc_set_trigger()
|
||||
* and \ref dacc_disable_trigger().
|
||||
* -# Configure FIFO transfer mode with \ref dacc_set_transfer_mode().
|
||||
* -# Control interrupts with \ref dacc_enable_interrupt(),
|
||||
* \ref dacc_disable_interrupt(), \ref dacc_get_interrupt_mask() and
|
||||
* \ref dacc_get_interrupt_status().
|
||||
* -# DACC registers support write protect with \ref dacc_set_writeprotect()
|
||||
* and \ref dacc_get_writeprotect_status().
|
||||
* -# If the DACC can work with PDC, use \ref dacc_get_pdc_base() to get
|
||||
* PDC register base for the DAC controller.
|
||||
* -# If the DACC has several channels to process, the following functions can
|
||||
* be used:
|
||||
* - Enable/Disable TAG and select output channel selection by
|
||||
* \ref dacc_set_channel_selection(),
|
||||
* \ref dacc_enable_flexible_channel_selection().
|
||||
* - Enable/disable channel by \ref dacc_enable_channel() /
|
||||
* \ref dacc_disable_channel(), get channel status by
|
||||
* \ref dacc_get_channel_status().
|
||||
*
|
||||
* \section dependencies Dependencies
|
||||
* This driver does not depend on other modules.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
//! Max channel number
|
||||
#if (SAM3N_SERIES)
|
||||
# define MAX_CH_NB 0
|
||||
#else
|
||||
# define MAX_CH_NB 1
|
||||
#endif
|
||||
|
||||
//! DACC Write Protect Key "DAC" in ASCII
|
||||
#define DACC_WP_KEY (0x444143)
|
||||
|
||||
/**
|
||||
* \brief Reset DACC.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*/
|
||||
void dacc_reset(Dacc *p_dacc)
|
||||
{
|
||||
p_dacc->DACC_CR = DACC_CR_SWRST;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable trigger and set the trigger source.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_trigger Trigger source number.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger)
|
||||
{
|
||||
uint32_t mr = p_dacc->DACC_MR & (~(DACC_MR_TRGSEL_Msk));
|
||||
#if (SAM3N_SERIES)
|
||||
p_dacc->DACC_MR = mr
|
||||
| DACC_MR_TRGEN
|
||||
| ((ul_trigger << DACC_MR_TRGSEL_Pos) & DACC_MR_TRGSEL_Msk);
|
||||
#else
|
||||
p_dacc->DACC_MR = mr | DACC_MR_TRGEN_EN | DACC_MR_TRGSEL(ul_trigger);
|
||||
#endif
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable trigger (free run mode).
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*/
|
||||
void dacc_disable_trigger(Dacc *p_dacc)
|
||||
{
|
||||
p_dacc->DACC_MR &= ~DACC_MR_TRGEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set the transfer mode.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_mode Transfer mode configuration.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_set_transfer_mode(Dacc *p_dacc, uint32_t ul_mode)
|
||||
{
|
||||
if (ul_mode) {
|
||||
#if (SAM3N_SERIES)
|
||||
p_dacc->DACC_MR |= DACC_MR_WORD;
|
||||
#else
|
||||
p_dacc->DACC_MR |= DACC_MR_WORD_WORD;
|
||||
#endif
|
||||
} else {
|
||||
#if (SAM3N_SERIES)
|
||||
p_dacc->DACC_MR &= (~DACC_MR_WORD);
|
||||
#else
|
||||
p_dacc->DACC_MR &= (~DACC_MR_WORD_WORD);
|
||||
#endif
|
||||
}
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable DACC interrupts.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_interrupt_mask The interrupt mask.
|
||||
*/
|
||||
void dacc_enable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask)
|
||||
{
|
||||
p_dacc->DACC_IER = ul_interrupt_mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable DACC interrupts.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_interrupt_mask The interrupt mask.
|
||||
*/
|
||||
void dacc_disable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask)
|
||||
{
|
||||
p_dacc->DACC_IDR = ul_interrupt_mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the interrupt mask.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return The interrupt mask.
|
||||
*/
|
||||
uint32_t dacc_get_interrupt_mask(Dacc *p_dacc)
|
||||
{
|
||||
return p_dacc->DACC_IMR;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the interrupt status.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return The interrupt status.
|
||||
*/
|
||||
uint32_t dacc_get_interrupt_status(Dacc *p_dacc)
|
||||
{
|
||||
return p_dacc->DACC_ISR;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Write data to conversion register.
|
||||
*
|
||||
* \note The \a ul_data could be output data or data with channel TAG when
|
||||
* flexible mode is used.
|
||||
*
|
||||
* In flexible mode the 2 bits, DACC_CDR[13:12] which are otherwise unused,
|
||||
* are employed to select the channel in the same way as with the USER_SEL
|
||||
* field. Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are
|
||||
* used for channel selection of the first data and the 2 bits,
|
||||
* DACC_CDR[29:28] for channel selection of the second data.
|
||||
*
|
||||
* \see dacc_enable_flexible_selection()
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_data The data to be transferred to analog value.
|
||||
*/
|
||||
void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data)
|
||||
{
|
||||
p_dacc->DACC_CDR = ul_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable or disable write protect of DACC registers.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_enable 1 to enable, 0 to disable.
|
||||
*/
|
||||
void dacc_set_writeprotect(Dacc *p_dacc, uint32_t ul_enable)
|
||||
{
|
||||
if (ul_enable) {
|
||||
p_dacc->DACC_WPMR = DACC_WPMR_WPKEY(DACC_WP_KEY)
|
||||
| DACC_WPMR_WPEN;
|
||||
} else {
|
||||
p_dacc->DACC_WPMR = DACC_WPMR_WPKEY(DACC_WP_KEY);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the write protect status.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return Write protect status.
|
||||
*/
|
||||
uint32_t dacc_get_writeprotect_status(Dacc *p_dacc)
|
||||
{
|
||||
return p_dacc->DACC_WPSR;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get PDC registers base address.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return DACC PDC register base address.
|
||||
*/
|
||||
Pdc *dacc_get_pdc_base(Dacc *p_dacc)
|
||||
{
|
||||
p_dacc = p_dacc;
|
||||
return PDC_DACC;
|
||||
}
|
||||
|
||||
#if (SAM3N_SERIES) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* \brief Enable DACC.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*/
|
||||
void dacc_enable(Dacc *p_dacc)
|
||||
{
|
||||
p_dacc->DACC_MR |= DACC_MR_DACEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable DACC.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
void dacc_disable(Dacc *p_dacc)
|
||||
{
|
||||
p_dacc->DACC_MR &= (~DACC_MR_DACEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set the DACC timing.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_startup Startup time selection.
|
||||
* \param ul_clock_divider Clock divider for internal trigger.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_startup,
|
||||
uint32_t ul_clock_divider)
|
||||
{
|
||||
uint32_t mr = p_dacc->DACC_MR
|
||||
& ~(DACC_MR_STARTUP_Msk | DACC_MR_CLKDIV_Msk);
|
||||
p_dacc->DACC_MR = mr | DACC_MR_STARTUP(ul_startup)
|
||||
| DACC_MR_CLKDIV(ul_clock_divider);
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
#endif /* #if (SAM3N_SERIES) */
|
||||
|
||||
#if (SAM3S_SERIES) || (SAM3XA_SERIES) || (SAM4S_SERIES) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* \brief Disable flexible (TAG) mode and select a channel for DAC outputs.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_channel Channel to select.
|
||||
*
|
||||
* \return \ref DACC_RC_OK if successful.
|
||||
*/
|
||||
uint32_t dacc_set_channel_selection(Dacc *p_dacc, uint32_t ul_channel)
|
||||
{
|
||||
uint32_t mr = p_dacc->DACC_MR & (~DACC_MR_USER_SEL_Msk);
|
||||
if (ul_channel > MAX_CH_NB) {
|
||||
return DACC_RC_INVALID_PARAM;
|
||||
}
|
||||
mr &= ~(DACC_MR_TAG);
|
||||
mr |= ul_channel << DACC_MR_USER_SEL_Pos;
|
||||
p_dacc->DACC_MR = mr;
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable the flexible channel selection mode (TAG).
|
||||
*
|
||||
* In this mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, are
|
||||
* employed to select the channel in the same way as with the USER_SEL field.
|
||||
* Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are used
|
||||
* for channel selection of the first data and the 2 bits, DACC_CDR[29:28]
|
||||
* for channel selection of the second data.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*/
|
||||
void dacc_enable_flexible_selection(Dacc *p_dacc)
|
||||
{
|
||||
p_dacc->DACC_MR |= DACC_MR_TAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set the power save mode.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_sleep_mode Sleep mode configuration.
|
||||
* \param ul_fast_wakeup_mode Fast wakeup mode configuration.
|
||||
*
|
||||
* \return \ref DACC_RC_OK if successful.
|
||||
*/
|
||||
uint32_t dacc_set_power_save(Dacc *p_dacc,
|
||||
uint32_t ul_sleep_mode, uint32_t ul_fast_wakeup_mode)
|
||||
{
|
||||
if (ul_sleep_mode) {
|
||||
p_dacc->DACC_MR |= DACC_MR_SLEEP;
|
||||
} else {
|
||||
p_dacc->DACC_MR &= (~DACC_MR_SLEEP);
|
||||
}
|
||||
if (ul_fast_wakeup_mode) {
|
||||
p_dacc->DACC_MR |= DACC_MR_FASTWKUP;
|
||||
} else {
|
||||
p_dacc->DACC_MR &= (~DACC_MR_FASTWKUP);
|
||||
}
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set DACC timings.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_refresh Refresh period setting value.
|
||||
* \param ul_maxs Max speed mode configuration.
|
||||
* \param ul_startup Startup time selection.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_set_timing(Dacc *p_dacc,
|
||||
uint32_t ul_refresh, uint32_t ul_maxs, uint32_t ul_startup)
|
||||
{
|
||||
uint32_t mr = p_dacc->DACC_MR
|
||||
& (~(DACC_MR_REFRESH_Msk | DACC_MR_STARTUP_Msk));
|
||||
mr |= DACC_MR_REFRESH(ul_refresh);
|
||||
if (ul_maxs) {
|
||||
mr |= DACC_MR_MAXS;
|
||||
} else {
|
||||
mr &= ~DACC_MR_MAXS;
|
||||
}
|
||||
mr |= (DACC_MR_STARTUP_Msk & ((ul_startup) << DACC_MR_STARTUP_Pos));
|
||||
p_dacc->DACC_MR = mr;
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable DACC channel.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_channel The output channel to enable.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_enable_channel(Dacc *p_dacc, uint32_t ul_channel)
|
||||
{
|
||||
if (ul_channel > MAX_CH_NB)
|
||||
return DACC_RC_INVALID_PARAM;
|
||||
|
||||
p_dacc->DACC_CHER = DACC_CHER_CH0 << ul_channel;
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable DACC channel.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_channel The output channel to disable.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_disable_channel(Dacc *p_dacc, uint32_t ul_channel)
|
||||
{
|
||||
if (ul_channel > MAX_CH_NB) {
|
||||
return DACC_RC_INVALID_PARAM;
|
||||
}
|
||||
p_dacc->DACC_CHDR = DACC_CHDR_CH0 << ul_channel;
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the channel status.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return DACC channel status.
|
||||
*/
|
||||
uint32_t dacc_get_channel_status(Dacc *p_dacc)
|
||||
{
|
||||
return p_dacc->DACC_CHSR;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set the analog control value.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
* \param ul_analog_control Analog control configuration.
|
||||
*
|
||||
* \return \ref DACC_RC_OK for OK.
|
||||
*/
|
||||
uint32_t dacc_set_analog_control(Dacc *p_dacc, uint32_t ul_analog_control)
|
||||
{
|
||||
p_dacc->DACC_ACR = ul_analog_control;
|
||||
return DACC_RC_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the analog control value.
|
||||
*
|
||||
* \param p_dacc Pointer to a DACC instance.
|
||||
*
|
||||
* \return Current setting of analog control.
|
||||
*/
|
||||
uint32_t dacc_get_analog_control(Dacc *p_dacc)
|
||||
{
|
||||
return p_dacc->DACC_ACR;
|
||||
}
|
||||
#endif /* (SAM3S_SERIES) || (SAM3XA_SERIES) */
|
||||
|
||||
//@}
|
||||
|
||||
/// @cond 0
|
||||
/**INDENT-OFF**/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**INDENT-ON**/
|
||||
/// @endcond
|
||||
Binary file not shown.
@ -72,6 +72,7 @@ pmc.o:
|
||||
00000000 T pmc_switch_udpck_to_upllck
|
||||
|
||||
pwmc.o:
|
||||
00000000 r C.9.7204
|
||||
00000000 t FindClockConfiguration
|
||||
00000000 T PWMC_ConfigureChannel
|
||||
00000000 T PWMC_ConfigureChannelExt
|
||||
@ -99,14 +100,14 @@ pwmc.o:
|
||||
00000000 T PWMC_SetSyncChannelUpdateUnlock
|
||||
00000000 T PWMC_WriteBuffer
|
||||
U __assert_func
|
||||
00000000 r __func__.3192
|
||||
00000000 r __func__.3203
|
||||
00000000 r __func__.3218
|
||||
00000000 r __func__.3229
|
||||
00000000 r __func__.3240
|
||||
00000000 r __func__.3247
|
||||
00000000 r __func__.3331
|
||||
00000000 r __func__.3337
|
||||
00000000 r __func__.5914
|
||||
00000000 r __func__.5925
|
||||
00000000 r __func__.5940
|
||||
00000000 r __func__.5951
|
||||
00000000 r __func__.5962
|
||||
00000000 r __func__.5969
|
||||
00000000 r __func__.6053
|
||||
00000000 r __func__.6059
|
||||
|
||||
rtc.o:
|
||||
00000000 T RTC_ClearSCCR
|
||||
@ -122,9 +123,9 @@ rtc.o:
|
||||
00000000 T RTC_SetTime
|
||||
00000000 T RTC_SetTimeAlarm
|
||||
U __assert_func
|
||||
00000000 r __func__.3189
|
||||
00000000 r __func__.3198
|
||||
00000000 r __func__.3203
|
||||
00000000 r __func__.5911
|
||||
00000000 r __func__.5920
|
||||
00000000 r __func__.5925
|
||||
|
||||
rtt.o:
|
||||
00000000 T RTT_EnableIT
|
||||
@ -133,8 +134,8 @@ rtt.o:
|
||||
00000000 T RTT_SetAlarm
|
||||
00000000 T RTT_SetPrescaler
|
||||
U __assert_func
|
||||
00000000 r __func__.3196
|
||||
00000000 r __func__.3204
|
||||
00000000 r __func__.5918
|
||||
00000000 r __func__.5926
|
||||
|
||||
spi.o:
|
||||
00000000 T SPI_Configure
|
||||
@ -155,9 +156,9 @@ tc.o:
|
||||
00000000 T TC_Start
|
||||
00000000 T TC_Stop
|
||||
U __assert_func
|
||||
00000000 r __func__.3191
|
||||
00000000 r __func__.3197
|
||||
00000000 r __func__.3203
|
||||
00000000 r __func__.5913
|
||||
00000000 r __func__.5919
|
||||
00000000 r __func__.5925
|
||||
|
||||
timetick.o:
|
||||
00000000 T GetTickCount
|
||||
@ -184,18 +185,18 @@ twi.o:
|
||||
00000000 T TWI_TransferComplete
|
||||
00000000 T TWI_WriteByte
|
||||
U __assert_func
|
||||
00000000 r __func__.3556
|
||||
00000000 r __func__.3571
|
||||
00000000 r __func__.3575
|
||||
00000000 r __func__.3582
|
||||
00000000 r __func__.3586
|
||||
00000000 r __func__.3591
|
||||
00000000 r __func__.3599
|
||||
00000000 r __func__.3613
|
||||
00000000 r __func__.3618
|
||||
00000000 r __func__.3622
|
||||
00000000 r __func__.3627
|
||||
00000000 r __func__.3631
|
||||
00000000 r __func__.6286
|
||||
00000000 r __func__.6301
|
||||
00000000 r __func__.6305
|
||||
00000000 r __func__.6312
|
||||
00000000 r __func__.6316
|
||||
00000000 r __func__.6321
|
||||
00000000 r __func__.6329
|
||||
00000000 r __func__.6343
|
||||
00000000 r __func__.6348
|
||||
00000000 r __func__.6352
|
||||
00000000 r __func__.6357
|
||||
00000000 r __func__.6361
|
||||
|
||||
usart.o:
|
||||
00000000 T USART_Configure
|
||||
@ -214,7 +215,7 @@ usart.o:
|
||||
00000000 T USART_Write
|
||||
00000000 T USART_WriteBuffer
|
||||
U __assert_func
|
||||
00000000 r __func__.3477
|
||||
00000000 r __func__.6207
|
||||
|
||||
wdt.o:
|
||||
00000000 T WDT_Disable
|
||||
@ -379,3 +380,26 @@ uotghs.o:
|
||||
|
||||
interrupt_sam_nvic.o:
|
||||
00000000 D g_interrupt_enabled
|
||||
|
||||
dacc.o:
|
||||
00000000 T dacc_disable_channel
|
||||
00000000 T dacc_disable_interrupt
|
||||
00000000 T dacc_disable_trigger
|
||||
00000000 T dacc_enable_channel
|
||||
00000000 T dacc_enable_flexible_selection
|
||||
00000000 T dacc_enable_interrupt
|
||||
00000000 T dacc_get_analog_control
|
||||
00000000 T dacc_get_channel_status
|
||||
00000000 T dacc_get_interrupt_mask
|
||||
00000000 T dacc_get_interrupt_status
|
||||
00000000 T dacc_get_pdc_base
|
||||
00000000 T dacc_get_writeprotect_status
|
||||
00000000 T dacc_reset
|
||||
00000000 T dacc_set_analog_control
|
||||
00000000 T dacc_set_channel_selection
|
||||
00000000 T dacc_set_power_save
|
||||
00000000 T dacc_set_timing
|
||||
00000000 T dacc_set_transfer_mode
|
||||
00000000 T dacc_set_trigger
|
||||
00000000 T dacc_set_writeprotect
|
||||
00000000 T dacc_write_conversion_data
|
||||
|
||||
@ -161,10 +161,16 @@ static const uint8_t A8 = 62;
|
||||
static const uint8_t A9 = 63;
|
||||
static const uint8_t A10 = 64;
|
||||
static const uint8_t A11 = 65;
|
||||
static const uint8_t A12 = 66;
|
||||
static const uint8_t A13 = 67;
|
||||
static const uint8_t A14 = 68;
|
||||
static const uint8_t A15 = 69;
|
||||
static const uint8_t DA0 = 66;
|
||||
static const uint8_t DA1 = 67;
|
||||
static const uint8_t CANRX0 = 68;
|
||||
static const uint8_t CANTX0 = 69;
|
||||
|
||||
/*
|
||||
* DACC
|
||||
*/
|
||||
#define DACC_INTERFACE DACC
|
||||
#define DACC_INTERFACE_ID ID_DACC
|
||||
|
||||
/*
|
||||
* PWM
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user