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Add test J/K/packet/SE0_NAK, for usb.org process
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@ -91,6 +91,15 @@ const DeviceDescriptor USB_DeviceDescriptorA =
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const DeviceDescriptor USB_DeviceQualifier =
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D_QUALIFIER(0x00,0x00,0x00,64,1);
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//! 7.1.20 Test Mode Support
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static const unsigned char test_packet_buffer[] = {
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9
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0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8
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0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJJJKKKK * 8
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0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8
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0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8
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0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK * 10}, JK
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};
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//==================================================================
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//==================================================================
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@ -183,7 +192,7 @@ uint32_t USBD_Send(uint32_t ep, const void* d, uint32_t len)
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while (len)
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{
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if(ep==0) n= EP0_SIZE;
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if(ep==0) n = EP0_SIZE;
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else n = EPX_SIZE;
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if (n > len)
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n = len;
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@ -435,6 +444,129 @@ static bool USBD_SendDescriptor(Setup& setup)
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return true;
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}
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static void USB_SendZlp( void )
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{
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while( UOTGHS_DEVEPTISR_TXINI != (UOTGHS->UOTGHS_DEVEPTISR[0] & UOTGHS_DEVEPTISR_TXINI ) )
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{
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if((UOTGHS->UOTGHS_DEVISR & UOTGHS_DEVISR_SUSP) == UOTGHS_DEVISR_SUSP)
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{
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return;
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}
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}
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UOTGHS->UOTGHS_DEVEPTICR[0] = UOTGHS_DEVEPTICR_TXINIC;
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}
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static void Test_Mode_Support( uint8_t wIndex )
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{
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uint8_t i;
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(2);
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switch( wIndex )
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{
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case 4:
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//Test mode Test_Packet:
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//Upon command, a port must repetitively transmit the following test packet until
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//the exit action is taken. This enables the testing of rise and fall times, eye
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//patterns, jitter, and any other dynamic waveform specifications.
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//The test packet is made up by concatenating the following strings.
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//(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one
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//transmitted. “S” indicates that a bit stuff occurs, which inserts an “extra” NRZI data bit.
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//“* N” is used to indicate N occurrences of a string of bits or symbols.)
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//A port in Test_Packet mode must send this packet repetitively. The inter-packet timing
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//must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and
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//no greater than 125 us.
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// Send ZLP
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USB_SendZlp();
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UOTGHS->UOTGHS_DEVDMA[0].UOTGHS_DEVDMACONTROL = 0; // raz
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UOTGHS->UOTGHS_DEVDMA[1].UOTGHS_DEVDMACONTROL = 0; // raz
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// Configure endpoint 2, 64 bytes, direction IN, type BULK, 1 bank
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UOTGHS->UOTGHS_DEVEPTCFG[2] = UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE
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| UOTGHS_DEVEPTCFG_EPDIR_IN
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| UOTGHS_DEVEPTCFG_EPTYPE_BLK
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| UOTGHS_DEVEPTCFG_EPBK_1_BANK;
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// Check if the configuration is ok
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UOTGHS->UOTGHS_DEVEPTCFG[2] |= UOTGHS_DEVEPTCFG_ALLOC;
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while((UOTGHS->UOTGHS_DEVEPTISR[2]&UOTGHS_DEVEPTISR_CFGOK)==0) {}
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UOTGHS->UOTGHS_DEVEPT |= UOTGHS_DEVEPT_EPEN2;
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// Write FIFO
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for( i=0; i<sizeof(test_packet_buffer); i++)
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{
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ptr_dest[i] = test_packet_buffer[i];;
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}
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// Tst PACKET
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_TSTPCKT;
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// Send packet
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UOTGHS->UOTGHS_DEVEPTICR[2] = UOTGHS_DEVEPTICR_TXINIC;
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UOTGHS->UOTGHS_DEVEPTIDR[2] = UOTGHS_DEVEPTIDR_FIFOCONC;
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for(;;);
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// break;
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case 1:
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//Test mode Test_J:
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//Upon command, a port’s transceiver must enter the high-speed J state and remain in that
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//state until the exit action is taken. This enables the testing of the high output drive
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//level on the D+ line.
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// Send a ZLP
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USB_SendZlp();
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_TSTJ;
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for(;;);
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// break;
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case 2:
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//Test mode Test_K:
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//Upon command, a port’s transceiver must enter the high-speed K state and remain in
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//that state until the exit action is taken. This enables the testing of the high output drive
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//level on the D- line.
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// Send a ZLP
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USB_SendZlp();
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_TSTK;
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for(;;);
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// break;
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case 3:
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//Test mode Test_SE0_NAK:
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//Upon command, a port’s transceiver must enter the high-speed receive mode
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//and remain in that mode until the exit action is taken. This enables the testing
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//of output impedance, low level output voltage, and loading characteristics.
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//In addition, while in this mode, upstream facing ports (and only upstream facing ports)
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//must respond to any IN token packet with a NAK handshake (only if the packet CRC is
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//determined to be correct) within the normal allowed device response time. This enables testing of
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//the device squelch level circuitry and, additionally, provides a general purpose stimulus/response
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//test for basic functional testing.
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// Send a ZLP
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USB_SendZlp();
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UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SUSPEC
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| UOTGHS_DEVIDR_MSOFEC
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| UOTGHS_DEVIDR_SOFEC
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| UOTGHS_DEVIDR_EORSTEC
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| UOTGHS_DEVIDR_WAKEUPEC
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| UOTGHS_DEVIDR_EORSMEC
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| UOTGHS_DEVIDR_UPRSMEC
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| UOTGHS_DEVIDR_PEP_0
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| UOTGHS_DEVIDR_PEP_1
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| UOTGHS_DEVIDR_PEP_2
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| UOTGHS_DEVIDR_PEP_3
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| UOTGHS_DEVIDR_PEP_4
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| UOTGHS_DEVIDR_PEP_5
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| UOTGHS_DEVIDR_PEP_6
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| UOTGHS_DEVIDR_DMA_1
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| UOTGHS_DEVIDR_DMA_2
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| UOTGHS_DEVIDR_DMA_3
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| UOTGHS_DEVIDR_DMA_4
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| UOTGHS_DEVIDR_DMA_5
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| UOTGHS_DEVIDR_DMA_6;
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for(;;);
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// break;
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}
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}
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//unsigned int iii=0;
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// Endpoint 0 interrupt
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static void USB_ISR(void)
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@ -529,7 +661,7 @@ static void USB_ISR(void)
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// Check if the endpoint if currently halted
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if( isEndpointHalt == 1 )
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UDD_Send8(EP0, 1); // TODO
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else
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else
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UDD_Send8(EP0, 0); // TODO
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UDD_Send8(EP0, 0);
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}
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@ -548,7 +680,7 @@ static void USB_ISR(void)
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}
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else // if( setup.wValueL == 0) // ENDPOINTHALT
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{
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isEndpointHalt = 0; // TODO
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isEndpointHalt = 0; // TODO
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UDD_Send8(EP0, 0);
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UDD_Send8(EP0, 0);
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}
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@ -573,7 +705,17 @@ static void USB_ISR(void)
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if( setup.wValueL == 2) // TEST_MODE
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{
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// 7.1.20 Test Mode Support, 9.4.9 SetFeature
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// TODO
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if( (setup.bmRequestType == 0 /*USBGenericRequest_DEVICE*/) &&
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((setup.wIndex & 0x000F) == 0) )
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{
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// the lower byte of wIndex must be zero
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// the most significant byte of wIndex is used to specify the specific test mode
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UOTGHS->UOTGHS_DEVIDR &= ~UOTGHS_DEVIDR_SUSPEC;
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED; // remove suspend ?
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Test_Mode_Support( (setup.wIndex & 0xFF00)>>8 );
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}
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}
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}
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else if (SET_ADDRESS == r)
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