From 50f9e539d8b424842f4dab9d1357b30c6db3e0d8 Mon Sep 17 00:00:00 2001 From: Peter Van Hoyweghen Date: Tue, 14 Jul 2015 21:20:39 +0200 Subject: [PATCH] Ensure minimum spi pulse width. --- .../examples/11.ArduinoISP/ArduinoISP/ArduinoISP.ino | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/build/shared/examples/11.ArduinoISP/ArduinoISP/ArduinoISP.ino b/build/shared/examples/11.ArduinoISP/ArduinoISP/ArduinoISP.ino index eddeb11cb..5c3144ba5 100644 --- a/build/shared/examples/11.ArduinoISP/ArduinoISP/ArduinoISP.ino +++ b/build/shared/examples/11.ArduinoISP/ArduinoISP/ArduinoISP.ino @@ -114,6 +114,10 @@ class BitBangedSPI { } void begin() { + // slow enough for an attiny85 @ 1MHz + // (pulseWidth should be > 2 cpu cycles, so take 3 cycles:) + pulseWidth = 3; + pinMode(MISO, INPUT); pinMode(RESET, OUTPUT); pinMode(SCK, OUTPUT); @@ -126,11 +130,16 @@ class BitBangedSPI { for (unsigned int i = 0; i < 8; ++i) { digitalWrite(MOSI, b & 0x80); digitalWrite(SCK, HIGH); + delayMicroseconds(pulseWidth); b = (b << 1) | digitalRead(MISO); digitalWrite(SCK, LOW); // slow pulse + delayMicroseconds(pulseWidth); } return b; } + + private: + unsigned long pulseWidth; // in microseconds }; static BitBangedSPI SPI;