diff --git a/hardware/sam/cores/sam/Arduino.h b/hardware/sam/cores/sam/Arduino.h index eecd19467..0d0c34a91 100644 --- a/hardware/sam/cores/sam/Arduino.h +++ b/hardware/sam/cores/sam/Arduino.h @@ -53,13 +53,15 @@ extern void loop( void ) ; // // These perform slightly better as macros compared to inline functions // -#define digitalPinToPort( ulPin ) ( g_APinDescription[ulPin]->pPort ) -#define digitalPinToBitMask( ulPin ) ( g_APinDescription[ulPin]->dwPin ) +#define digitalPinToPort( ulPin ) ( g_APinDescription[ulPin].pPort ) +#define digitalPinToBitMask( ulPin ) ( g_APinDescription[ulPin].dwPin ) +/* #define digitalPinToTimer( P ) ( ) #define analogInPinToBit( P ) ( P ) #define portOutputRegister( P ) ( ) #define portInputRegister( P ) ( ) #define portModeRegister( P ) ( ) +*/ //#define NOT_A_PIN 0 // defined in pio.h/EPioType #define NOT_A_PORT 0 diff --git a/hardware/sam/cores/sam/validation/test.cpp b/hardware/sam/cores/sam/validation/test.cpp index 4ce8be845..7da0fec1a 100644 --- a/hardware/sam/cores/sam/validation/test.cpp +++ b/hardware/sam/cores/sam/validation/test.cpp @@ -76,6 +76,6 @@ void loop( void ) delay( 1000 ) ; // wait for a second Serial.write( '-' ) ; // send a char - Serial.write( "test1\n" ) ; // send a string - Serial.write( "test2" ) ; // send another string +// Serial.write( "test1\n" ) ; // send a string +// Serial.write( "test2" ) ; // send another string } diff --git a/hardware/sam/cores/sam/wiring_analog.c b/hardware/sam/cores/sam/wiring_analog.c new file mode 100644 index 000000000..825eb3176 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_analog.c @@ -0,0 +1,136 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +//#include "wiring_private.h" +#include "Arduino.h" + +#ifdef __cplusplus + extern "C" { +#endif + + +eAnalogReference analog_reference = AR_DEFAULT ; + +void analogReference( eAnalogReference ulMode ) +{ + analog_reference = ulMode ; +} + +uint32_t analogRead( uint32_t ulPin ) +{ + uint32_t ulValue ; + uint32_t ulChannel ; + + ulChannel=g_APinDescription[ulPin].ulAnalogChannel ; + +#if defined sam3u_ek +#elif defined sam3s_ek +#elif defined arduino_due + + switch ( ulChannel ) + { + // Handling ADC 10 bits channels + case ADC0 : + case ADC1 : + case ADC2 : + case ADC3 : + case ADC4 : + case ADC5 : + case ADC6 : + case ADC7 : + adc_enable_channel( ADC, ulChannel ) ; + adc_start( ADC ) ; + adc_get_value( ADC, ulChannel ) ; + adc_stop( ADC ) ; + break ; + + // Handling ADC 12 bits channels + case ADC8 : + case ADC9 : + case ADC10 : + case ADC11 : + case ADC12 : + case ADC13 : + case ADC14 : + case ADC15 : + adc12_enable_channel( ADC12B, ulChannel-ADC8 ) ; + adc12_start( ADC12B ) ; + adc12_get_value( ADC12B, ulChannel-ADC8 ) ; + adc12_stop( ADC12B ) ; + break ; + + // Compiler could yell because we don't handle DAC pins + default : + break ; + } +#endif + + + + return ulValue ; +} + +// Right now, PWM output only works on the pins with +// hardware support. These are defined in the appropriate +// pins_*.c file. For the rest of the pins, we default +// to digital output. +void analogWrite( uint32_t ulPin, uint32_t ulValue ) +{ + pinMode( ulPin, OUTPUT ) ; + + if ( ulValue == 0 ) + { + digitalWrite( ulPin, LOW ) ; + } + else + { + if ( ulValue == 255) + { + digitalWrite( ulPin, HIGH ) ; + } + else + { + if ( (g_APinDescription[ulPin].ulPinAttribute && PIN_ATTR_PWM) == PIN_ATTR_PWM ) + { + // Setup PWM for this pin + } + else + { + if ( (g_APinDescription[ulPin].ulPinAttribute && PIN_ATTR_TIMER) == PIN_ATTR_TIMER ) + { + // Setup Timer for this pin + } + else + { + if ( ulValue < 128 ) + { + digitalWrite( ulPin, LOW ) ; + } + else + { + digitalWrite( ulPin, HIGH ) ; + } + } + } + } + } +} + +#ifdef __cplusplus +} +#endif diff --git a/hardware/sam/cores/sam/wiring_analog.h b/hardware/sam/cores/sam/wiring_analog.h index 3eef89082..06a6a9d04 100644 --- a/hardware/sam/cores/sam/wiring_analog.h +++ b/hardware/sam/cores/sam/wiring_analog.h @@ -50,7 +50,9 @@ extern void analogWrite( uint32_t ulPin, uint32_t ulValue ) ; /* * \brief Reads the value from the specified analog pin. * - * \param ulValue + * \param ulPin + * + * \return Read value from selected pin, if no error. */ extern uint32_t analogRead( uint32_t ulPin ) ; diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h index eefe44af3..723107e76 100644 --- a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h @@ -65,8 +65,6 @@ typedef struct { RoReg Reserved6[26]; RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RoReg Reserved7[9]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ } Pmc; #endif /* __ASSEMBLY__ */ /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ @@ -96,13 +94,9 @@ typedef struct { #define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ #define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ #define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ #define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ #define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ #define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ #define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ #define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ #define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ @@ -127,13 +121,9 @@ typedef struct { #define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ #define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ #define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ #define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ #define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ #define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ #define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ #define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ #define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ @@ -158,13 +148,9 @@ typedef struct { #define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ #define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ #define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ #define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ #define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ #define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ #define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ #define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ #define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ @@ -214,7 +200,7 @@ typedef struct { #define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ #define PMC_MCKR_PRES_Pos 4 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ @@ -233,6 +219,13 @@ typedef struct { #define PMC_PCK_PRES_Pos 4 #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h index 644c758a1..8dfd17247 100644 --- a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h @@ -52,7 +52,6 @@ #define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ #define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ #define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ #else #define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ #define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ @@ -74,7 +73,6 @@ #define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ #define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ #define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ #endif /* __ASSEMBLY__ */ #endif /* _SAM3N_PMC_INSTANCE_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c index 0f62eb8f1..59b99d8a1 100644 --- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c +++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c @@ -28,11 +28,11 @@ extern "C" { /* Clock settings (48MHz) */ #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8)) -#define SYS_BOARD_PLLR (CKGR_PLLR_STUCKTO1 \ - | CKGR_PLLR_MUL(0x3) \ - | CKGR_PLLR_PLLCOUNT(0x3f) \ - | CKGR_PLLR_DIV(0x1)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLL_CLK) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ + | CKGR_PLLAR_MULA(0x3) \ + | CKGR_PLLAR_PLLACOUNT(0x3f) \ + | CKGR_PLLAR_DIVA(0x1)) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK) /* Clock Definitions */ #define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */ @@ -77,8 +77,8 @@ void SystemInit(void) } /* Initialize PLL */ - PMC->CKGR_PLLR = SYS_BOARD_PLLR; - while (!(PMC->PMC_SR & PMC_SR_LOCK)) { + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { } /* Switch to main clock */ @@ -95,28 +95,6 @@ void SystemInit(void) SystemCoreClock = CHIP_FREQ_CPU_MAX; } -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void) -{ - /* Set FWS for Embedded Flash Access according operating frequency*/ - if(SystemCoreClock < SYS_FREQ_FWS_0){ - EFC->EEFC_FMR = EEFC_FMR_FWS(0); - }else if(SystemCoreClock < SYS_FREQ_FWS_1){ - EFC->EEFC_FMR = EEFC_FMR_FWS(1); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC->EEFC_FMR = EEFC_FMR_FWS(2); - }else{ - EFC->EEFC_FMR = EEFC_FMR_FWS(3); - } - -#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT - /*Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif -} - void SystemCoreClockUpdate(void) { /* Determine clock frequency according to clock register values */ @@ -135,12 +113,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -148,29 +126,29 @@ void SystemCoreClockUpdate(void) } } break; - case PMC_MCKR_CSS_PLL_CLK: /* PLL clock */ + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { SystemCoreClock = SYS_FREQ_XTAL_XTAL12M; } else { SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: break; } } - SystemCoreClock *= ((((PMC->CKGR_PLLR) & CKGR_PLLR_MUL_Msk) >> - CKGR_PLLR_MUL_Pos) + 1U); - SystemCoreClock /= ((((PMC->CKGR_PLLR) & CKGR_PLLR_DIV_Msk) >> - CKGR_PLLR_DIV_Pos)); + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> + CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> + CKGR_PLLAR_DIVA_Pos)); break; } @@ -182,6 +160,28 @@ void SystemCoreClockUpdate(void) } } +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (dw_clk < SYS_FREQ_FWS_0) { + EFC->EEFC_FMR = EEFC_FMR_FWS(0); + } else if (dw_clk < SYS_FREQ_FWS_1) { + EFC->EEFC_FMR = EEFC_FMR_FWS(1); + } else if (dw_clk < SYS_FREQ_FWS_2) { + EFC->EEFC_FMR = EEFC_FMR_FWS(2); + } else { + EFC->EEFC_FMR = EEFC_FMR_FWS(3); + } + +#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h index cddf15cb6..a2427b239 100644 --- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h +++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h @@ -36,17 +36,17 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ */ void SystemInit(void); -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void); - /** * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ void SystemCoreClockUpdate(void); +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk); + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h index f74f1a35a..35e709b39 100644 --- a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h +++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h @@ -93,9 +93,6 @@ typedef struct { #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ #define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ #define HSMCI_DTOR_DTOCYC_Pos 0 #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h index 1a7b93b6c..c726e5569 100644 --- a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h @@ -234,7 +234,7 @@ typedef struct { #define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */ #define PMC_MCKR_PRES_Pos 4 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ @@ -255,11 +255,18 @@ typedef struct { #define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ #define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ #define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ -#define PMC_PCK_CSS_PLLB_CLKUPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ +#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ #define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ #define PMC_PCK_PRES_Pos 4 #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c index e9f3567c7..93d837d10 100644 --- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c +++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c @@ -15,11 +15,6 @@ #include "../exceptions.h" #include "sam3.h" -/* Stack Configuration */ -#define STACK_SIZE 0x900 /** Stack size (in DWords) */ -__attribute__ ((aligned(8), section(".stack"))) -uint32_t pdwStack[STACK_SIZE]; - /* Initialize segments */ extern uint32_t _sfixed; extern uint32_t _efixed; @@ -28,6 +23,8 @@ extern uint32_t _srelocate; extern uint32_t _erelocate; extern uint32_t _szero; extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; /** \cond DOXYGEN_SHOULD_SKIP_THIS */ int main(void); @@ -40,7 +37,7 @@ __attribute__ ((section(".vectors"))) IntFunc exception_table[] = { /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc) (&pdwStack[STACK_SIZE - 1]), + (IntFunc) (&_estack), Reset_Handler, NMI_Handler, diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c index 2a69a8ad1..6219a6437 100644 --- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c +++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c @@ -27,11 +27,11 @@ extern "C" { /* Clock Settings (64MHz) */ #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U)) -#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \ +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ | CKGR_PLLAR_MULA(0xfU) \ | CKGR_PLLAR_PLLACOUNT(0x3fU) \ | CKGR_PLLAR_DIVA(0x3U)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK) /* Clock Definitions */ #define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */ @@ -92,28 +92,6 @@ void SystemInit(void) SystemCoreClock = CHIP_FREQ_CPU_MAX; } -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void) -{ - /* Set FWS for Embedded Flash Access according operating frequency*/ - if(SystemCoreClock < SYS_FREQ_FWS_0){ - EFC->EEFC_FMR = EEFC_FMR_FWS(0); - }else if(SystemCoreClock < SYS_FREQ_FWS_1){ - EFC->EEFC_FMR = EEFC_FMR_FWS(1); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC->EEFC_FMR = EEFC_FMR_FWS(2); - }else{ - EFC->EEFC_FMR = EEFC_FMR_FWS(3); - } - -#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT - /*Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif -} - void SystemCoreClockUpdate(void) { /* Determine clock frequency according to clock register values */ @@ -132,12 +110,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -153,12 +131,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -188,6 +166,28 @@ void SystemCoreClockUpdate(void) } } +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (dw_clk < SYS_FREQ_FWS_0) { + EFC->EEFC_FMR = EEFC_FMR_FWS(0); + } else if (dw_clk < SYS_FREQ_FWS_1) { + EFC->EEFC_FMR = EEFC_FMR_FWS(1); + } else if (dw_clk < SYS_FREQ_FWS_2) { + EFC->EEFC_FMR = EEFC_FMR_FWS(2); + } else { + EFC->EEFC_FMR = EEFC_FMR_FWS(3); + } + +#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h index ba5b83fb0..e5c32e9c4 100644 --- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h +++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h @@ -36,17 +36,17 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ */ void SystemInit(void); -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void); - /** * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ void SystemCoreClockUpdate(void); +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk); + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h index b83a13b0b..4132a460b 100644 --- a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h +++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h @@ -93,9 +93,6 @@ typedef struct { #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ #define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ #define HSMCI_DTOR_DTOCYC_Pos 0 #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ @@ -380,10 +377,6 @@ typedef struct { /* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ #define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ #define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ -/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ -#define HSMCI_FIFO_DATA_Pos 0 -#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ -#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) /*@}*/ diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h index cd1d7288a..47cca67d0 100644 --- a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h @@ -106,7 +106,6 @@ typedef struct { #define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ #define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ #define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ #define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ #define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ #define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ @@ -137,7 +136,6 @@ typedef struct { #define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ #define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ #define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ #define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ #define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ #define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ @@ -168,7 +166,6 @@ typedef struct { #define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ #define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ #define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ #define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ #define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ #define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ @@ -236,7 +233,7 @@ typedef struct { #define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */ #define PMC_MCKR_PRES_Pos 4 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ @@ -257,11 +254,18 @@ typedef struct { #define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ #define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ #define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ -#define PMC_PCK_CSS_PLLB_CLKUPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ +#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ #define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ #define PMC_PCK_PRES_Pos 4 #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ @@ -362,101 +366,14 @@ typedef struct { #define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ #define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ #define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ /* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ #define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ #define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ #define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ /* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ #define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ #define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ #define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ /* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ #define PMC_OCR_CAL4_Pos 0 #define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c index e616b8d6c..67c3d62b4 100644 --- a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c +++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c @@ -15,11 +15,6 @@ #include "../exceptions.h" #include "sam3.h" -/* Stack Configuration */ -#define STACK_SIZE 0x900 /** Stack size (in DWords) */ -__attribute__ ((aligned(8), section(".stack"))) -uint32_t pdwStack[STACK_SIZE]; - /* Initialize segments */ extern uint32_t _sfixed; extern uint32_t _efixed; @@ -28,6 +23,8 @@ extern uint32_t _srelocate; extern uint32_t _erelocate; extern uint32_t _szero; extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; /** \cond DOXYGEN_SHOULD_SKIP_THIS */ int main(void); @@ -40,7 +37,7 @@ __attribute__ ((section(".vectors"))) IntFunc exception_table[] = { /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc) (&pdwStack[STACK_SIZE - 1]), + (IntFunc) (&_estack), Reset_Handler, NMI_Handler, diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c index 2517ce859..507f74499 100644 --- a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c +++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c @@ -28,11 +28,11 @@ extern "C" { /* Clock settings (64MHz) */ #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8)) -#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \ +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ | CKGR_PLLAR_MULA(0xf) \ | CKGR_PLLAR_PLLACOUNT(0x3f) \ | CKGR_PLLAR_DIVA(0x3)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK) /* Clock Definitions */ #define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */ @@ -92,28 +92,6 @@ void SystemInit(void) SystemCoreClock = CHIP_FREQ_CPU_MAX; } -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void) -{ - /* Set FWS for Embedded Flash Access according operating frequency*/ - if(SystemCoreClock < SYS_FREQ_FWS_0){ - EFC->EEFC_FMR = EEFC_FMR_FWS(0); - }else if(SystemCoreClock < SYS_FREQ_FWS_1){ - EFC->EEFC_FMR = EEFC_FMR_FWS(1); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC->EEFC_FMR = EEFC_FMR_FWS(2); - }else{ - EFC->EEFC_FMR = EEFC_FMR_FWS(3); - } - -#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT - /*Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif -} - void SystemCoreClockUpdate(void) { /* Determine clock frequency according to clock register values */ @@ -132,12 +110,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -153,12 +131,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -187,6 +165,28 @@ void SystemCoreClockUpdate(void) } } +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (dw_clk < SYS_FREQ_FWS_0) { + EFC->EEFC_FMR = EEFC_FMR_FWS(0); + } else if (dw_clk < SYS_FREQ_FWS_1) { + EFC->EEFC_FMR = EEFC_FMR_FWS(1); + } else if (dw_clk < SYS_FREQ_FWS_2) { + EFC->EEFC_FMR = EEFC_FMR_FWS(2); + } else { + EFC->EEFC_FMR = EEFC_FMR_FWS(3); + } + +#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h index c8af222fd..b40962425 100644 --- a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h +++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h @@ -36,17 +36,17 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ */ void SystemInit(void); -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void); - /** * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ void SystemCoreClockUpdate(void); +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk); + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h index c01c16b30..d83700636 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h +++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h @@ -69,11 +69,23 @@ typedef struct { #define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ /* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ #define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ #define ADC_MR_TRGSEL_Pos 1 #define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ #define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos))) +#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */ +#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */ +#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */ +#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */ #define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_BITS_10 (0x0u << 4) /**< \brief (ADC_MR) 10-bit resolution */ +#define ADC_MR_LOWRES_BITS_8 (0x1u << 4) /**< \brief (ADC_MR) 8-bit resolution */ #define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ +#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */ #define ADC_MR_PRESCAL_Pos 8 #define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ #define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) @@ -200,6 +212,10 @@ typedef struct { /* -------- ADC_CDR[8] : (ADC Offset: 0x30) Channel Data Register -------- */ #define ADC_CDR_DATA_Pos 0 #define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_IBCTL_Pos 8 +#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */ +#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) /* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ #define ADC_RPR_RXPTR_Pos 0 #define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h index 76bc0d9d3..21f72a1d8 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h +++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h @@ -76,6 +76,8 @@ typedef struct { #define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) /**< \brief (ADC12B_MR) Trigger Selection */ #define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos))) #define ADC12B_MR_LOWRES (0x1u << 4) /**< \brief (ADC12B_MR) Resolution */ +#define ADC12B_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC12B_MR) 10-bit resolution */ +#define ADC12B_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC12B_MR) 8-bit resolution */ #define ADC12B_MR_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode */ #define ADC12B_MR_PRESCAL_Pos 8 #define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) /**< \brief (ADC12B_MR) Prescaler Rate Selection */ diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h index d42208d2f..7f6afe5ba 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h +++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h @@ -81,9 +81,6 @@ typedef struct { #define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ #define HSMCI_DTOR_DTOCYC_Pos 0 #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h index 8bc0ffd80..6cd5dee7a 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h @@ -65,8 +65,6 @@ typedef struct { RoReg Reserved5[26]; RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RoReg Reserved6[9]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ } Pmc; #endif /* __ASSEMBLY__ */ /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ @@ -97,7 +95,6 @@ typedef struct { #define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ #define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ #define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ #define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ #define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ #define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ @@ -110,8 +107,6 @@ typedef struct { #define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ #define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ #define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ /* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ #define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ #define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ @@ -128,7 +123,6 @@ typedef struct { #define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ #define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ #define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ #define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ #define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ #define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ @@ -141,8 +135,6 @@ typedef struct { #define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ #define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ #define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ /* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ #define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ #define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ @@ -159,7 +151,6 @@ typedef struct { #define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ #define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ #define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ #define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ #define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ #define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ @@ -172,8 +163,6 @@ typedef struct { #define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ #define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ #define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ /* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ #define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ #define CKGR_UCKR_UPLLCOUNT_Pos 20 @@ -188,6 +177,7 @@ typedef struct { #define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */ #define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */ #define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) #define CKGR_MOR_MOSCXTST_Pos 8 #define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) @@ -218,9 +208,10 @@ typedef struct { #define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ #define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ #define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLLClock is selected */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) #define PMC_MCKR_PRES_Pos 4 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ @@ -241,10 +232,18 @@ typedef struct { #define PMC_PCK_PRES_Pos 4 #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ #define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ #define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ #define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ #define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ @@ -255,6 +254,7 @@ typedef struct { #define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ #define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ #define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ #define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ #define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ #define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ @@ -265,6 +265,7 @@ typedef struct { #define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ #define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ #define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ #define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ #define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ #define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ @@ -278,6 +279,7 @@ typedef struct { #define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ #define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ #define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ #define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ #define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ #define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h index 19bcafb02..da2468b96 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h @@ -53,7 +53,6 @@ #define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ #define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ #define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ #else #define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ #define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ @@ -76,7 +75,6 @@ #define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ #define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ #define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ #endif /* __ASSEMBLY__ */ #endif /* _SAM3U_PMC_INSTANCE_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c index e19290451..67b3a4c72 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c +++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c @@ -15,11 +15,6 @@ #include "../exceptions.h" #include "sam3.h" -/* Stack Configuration */ -#define STACK_SIZE 0x900 /** Stack size (in DWords) */ -__attribute__ ((aligned(8), section(".stack"))) -uint32_t pdwStack[STACK_SIZE]; - /* Initialize segments */ extern uint32_t _sfixed; extern uint32_t _efixed; @@ -28,6 +23,8 @@ extern uint32_t _srelocate; extern uint32_t _erelocate; extern uint32_t _szero; extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; /** \cond DOXYGEN_SHOULD_SKIP_THIS */ int main(void); @@ -40,7 +37,7 @@ __attribute__ ((section(".vectors"))) IntFunc exception_table[] = { /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc) (&pdwStack[STACK_SIZE - 1]), + (IntFunc) (&_estack), Reset_Handler, NMI_Handler, HardFault_Handler, diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c index e99a83c39..d4a492afa 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c +++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c @@ -28,11 +28,11 @@ extern "C" { /* Clock settings (96MHz) */ #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8)) -#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \ +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ | CKGR_PLLAR_MULA(0x7) \ | CKGR_PLLAR_PLLACOUNT(0x3f) \ | CKGR_PLLAR_DIVA(0x1)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK) /* Clock Definitions */ #define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */ @@ -96,35 +96,6 @@ void SystemInit(void) SystemCoreClock = CHIP_FREQ_CPU_MAX; } -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void) -{ - /* Set FWS for Embedded Flash Access according operating frequency*/ - if(SystemCoreClock < SYS_FREQ_FWS_0){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); - }else if(SystemCoreClock < SYS_FREQ_FWS_1){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(1); - EFC1->EEFC_FMR = EEFC_FMR_FWS(1); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(2); - EFC1->EEFC_FMR = EEFC_FMR_FWS(2); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(3); - EFC1->EEFC_FMR = EEFC_FMR_FWS(3); - }else{ - EFC0->EEFC_FMR = EEFC_FMR_FWS(4); - EFC1->EEFC_FMR = EEFC_FMR_FWS(4); - } - -#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT - /*Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif -} - void SystemCoreClockUpdate(void) { /* Determine clock frequency according to clock register values */ @@ -143,12 +114,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -164,12 +135,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -195,6 +166,35 @@ void SystemCoreClockUpdate(void) } } +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (dw_clk < SYS_FREQ_FWS_0) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); + } else if (dw_clk < SYS_FREQ_FWS_1) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(1); + EFC1->EEFC_FMR = EEFC_FMR_FWS(1); + } else if (dw_clk < SYS_FREQ_FWS_2) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(2); + EFC1->EEFC_FMR = EEFC_FMR_FWS(2); + } else if (dw_clk < SYS_FREQ_FWS_3) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(3); + EFC1->EEFC_FMR = EEFC_FMR_FWS(3); + } else { + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + } + +#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h index 9cee02b52..82c0118cd 100644 --- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h +++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h @@ -36,17 +36,17 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ */ void SystemInit(void); -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void); - /** * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ void SystemCoreClockUpdate(void); +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk); + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h index c56c94b28..ae43604d7 100644 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h +++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h @@ -81,9 +81,6 @@ typedef struct { #define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ #define HSMCI_DTOR_DTOCYC_Pos 0 #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h index 51a2551df..c33044455 100644 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h @@ -72,7 +72,6 @@ typedef struct { WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ RwReg PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ } Pmc; #endif /* __ASSEMBLY__ */ /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ @@ -229,7 +228,7 @@ typedef struct { #define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */ #define PMC_MCKR_PRES_Pos 4 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ @@ -255,10 +254,18 @@ typedef struct { #define PMC_PCK_PRES_Pos 4 #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ #define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ #define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ #define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ #define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ @@ -269,6 +276,7 @@ typedef struct { #define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ #define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ #define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ #define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ #define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ #define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ @@ -279,6 +287,7 @@ typedef struct { #define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ #define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ #define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ #define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ #define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ #define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ @@ -292,6 +301,7 @@ typedef struct { #define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ #define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ #define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ #define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ #define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ #define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ @@ -361,25 +371,6 @@ typedef struct { #define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ #define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ #define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ /* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ #define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ #define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ @@ -394,25 +385,6 @@ typedef struct { #define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ #define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ #define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ /* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ #define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ #define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ @@ -427,25 +399,6 @@ typedef struct { #define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ #define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ #define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ /* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ #define PMC_PCR_PID_Pos 0 #define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h index d08e59512..1c867c775 100644 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h +++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h @@ -58,7 +58,6 @@ #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ -#define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ #else #define REG_PMC_SCER (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ #define REG_PMC_SCDR (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ @@ -86,7 +85,6 @@ #define REG_PMC_PCDR1 (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ #define REG_PMC_PCSR1 (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ #define REG_PMC_PCR (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ -#define REG_PMC_OCR (*(RwReg*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ #endif /* __ASSEMBLY__ */ #endif /* _SAM3XA_PMC_INSTANCE_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2c.h deleted file mode 100644 index a43c75048..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2c.h +++ /dev/null @@ -1,358 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2C_PIO_ -#define _SAM3X2C_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 - -#endif /* _SAM3X2C_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2e.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2e.h deleted file mode 100644 index bfa0f2b3e..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2e.h +++ /dev/null @@ -1,552 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2E_PIO_ -#define _SAM3X2E_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ -#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ -#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ -#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ -#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ -#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ -#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ -#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ -#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ -#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ -#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ -#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ -#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ -#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ -#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ -#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ -#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ -#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ -#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ -#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ -#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ -#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ -#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ -#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ -#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ -#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ -#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ -#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ -#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ -#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ -#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ -#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ -#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ -#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ -#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ -#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ -#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ -#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ -#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ -#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ -#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ -#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ -#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ -#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ -#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ -#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ -#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ -#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ -#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ -#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ -#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ -#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ -#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ -#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ -#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ -#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ -#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ -#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ -#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ -#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ -#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ -#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ -#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ -#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ -#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ -#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ -#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ -#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ -#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ -#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 - -#endif /* _SAM3X2E_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2g.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2g.h deleted file mode 100644 index 55e4c5960..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2g.h +++ /dev/null @@ -1,680 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2G_PIO_ -#define _SAM3X2G_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ -#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ -#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ -#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ -#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ -#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ -#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ -#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ -#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ -#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ -#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ -#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ -#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ -#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ -#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ -#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ -#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ -#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ -#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ -#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ -#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ -#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ -#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ -#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ -#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ -#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ -#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */ -#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */ -#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */ -#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */ -#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */ -#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ -#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ -#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ -#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ -#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ -#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ -#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ -#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ -#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ -#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ -#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ -#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ -#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ -#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ -#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ -#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ -#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ -#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ -#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ -#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ -#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ -#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ -#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ -#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ -#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ -#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ -#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ -#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ -#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ -#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ -#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ -#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ -#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ -#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ -#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ -#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ -#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ -#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ -#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ -#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ -#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ -#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ -#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ -#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ -#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ -#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ -#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ -#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ -#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ -#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ -#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ -#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ -#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ -#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ -#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ -#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ -#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ -#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ -#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ -#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ -#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ -#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ -#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ -#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ -#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ -#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ -#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ -#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ -#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ -#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */ -#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */ -#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */ -#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ -#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ -#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ -#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 -#define PIO_PE6_IDX 134 -#define PIO_PE7_IDX 135 -#define PIO_PE8_IDX 136 -#define PIO_PE9_IDX 137 -#define PIO_PE10_IDX 138 -#define PIO_PE11_IDX 139 -#define PIO_PE12_IDX 140 -#define PIO_PE13_IDX 141 -#define PIO_PE14_IDX 142 -#define PIO_PE15_IDX 143 -#define PIO_PE16_IDX 144 -#define PIO_PE17_IDX 145 -#define PIO_PE18_IDX 146 -#define PIO_PE19_IDX 147 -#define PIO_PE20_IDX 148 -#define PIO_PE21_IDX 149 -#define PIO_PE22_IDX 150 -#define PIO_PE23_IDX 151 -#define PIO_PE24_IDX 152 -#define PIO_PE25_IDX 153 -#define PIO_PE26_IDX 154 -#define PIO_PE27_IDX 155 -#define PIO_PE28_IDX 156 -#define PIO_PE29_IDX 157 -#define PIO_PE30_IDX 158 -#define PIO_PE31_IDX 159 -#define PIO_PF0_IDX 160 -#define PIO_PF1_IDX 161 -#define PIO_PF2_IDX 162 -#define PIO_PF3_IDX 163 -#define PIO_PF4_IDX 164 -#define PIO_PF5_IDX 165 - -#endif /* _SAM3X2G_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2h.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2h.h deleted file mode 100644 index c3b3e7be5..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x2h.h +++ /dev/null @@ -1,680 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2H_PIO_ -#define _SAM3X2H_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ -#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ -#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ -#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ -#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ -#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ -#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ -#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ -#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ -#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ -#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ -#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ -#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ -#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ -#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ -#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ -#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ -#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ -#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ -#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ -#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ -#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ -#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ -#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ -#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ -#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ -#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */ -#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */ -#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */ -#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */ -#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */ -#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ -#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ -#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ -#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ -#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ -#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ -#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ -#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ -#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ -#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ -#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ -#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ -#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ -#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ -#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ -#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ -#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ -#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ -#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ -#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ -#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ -#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ -#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ -#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ -#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ -#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ -#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ -#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ -#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ -#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ -#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ -#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ -#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ -#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ -#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ -#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ -#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ -#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ -#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ -#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ -#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ -#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ -#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ -#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ -#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ -#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ -#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ -#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ -#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ -#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ -#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ -#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ -#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ -#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ -#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ -#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ -#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ -#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ -#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ -#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ -#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ -#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ -#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ -#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ -#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ -#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ -#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ -#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ -#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ -#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */ -#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */ -#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */ -#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ -#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ -#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ -#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 -#define PIO_PE6_IDX 134 -#define PIO_PE7_IDX 135 -#define PIO_PE8_IDX 136 -#define PIO_PE9_IDX 137 -#define PIO_PE10_IDX 138 -#define PIO_PE11_IDX 139 -#define PIO_PE12_IDX 140 -#define PIO_PE13_IDX 141 -#define PIO_PE14_IDX 142 -#define PIO_PE15_IDX 143 -#define PIO_PE16_IDX 144 -#define PIO_PE17_IDX 145 -#define PIO_PE18_IDX 146 -#define PIO_PE19_IDX 147 -#define PIO_PE20_IDX 148 -#define PIO_PE21_IDX 149 -#define PIO_PE22_IDX 150 -#define PIO_PE23_IDX 151 -#define PIO_PE24_IDX 152 -#define PIO_PE25_IDX 153 -#define PIO_PE26_IDX 154 -#define PIO_PE27_IDX 155 -#define PIO_PE28_IDX 156 -#define PIO_PE29_IDX 157 -#define PIO_PE30_IDX 158 -#define PIO_PE31_IDX 159 -#define PIO_PF0_IDX 160 -#define PIO_PF1_IDX 161 -#define PIO_PF2_IDX 162 -#define PIO_PF3_IDX 163 -#define PIO_PF4_IDX 164 -#define PIO_PF5_IDX 165 - -#endif /* _SAM3X2H_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4g.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4g.h deleted file mode 100644 index 6d3997d5f..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4g.h +++ /dev/null @@ -1,680 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X4G_PIO_ -#define _SAM3X4G_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ -#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ -#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ -#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ -#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ -#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ -#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ -#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ -#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ -#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ -#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ -#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ -#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ -#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ -#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ -#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ -#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ -#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ -#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ -#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ -#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ -#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ -#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ -#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ -#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ -#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ -#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */ -#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */ -#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */ -#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */ -#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */ -#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ -#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ -#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ -#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ -#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ -#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ -#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ -#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ -#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ -#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ -#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ -#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ -#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ -#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ -#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ -#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ -#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ -#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ -#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ -#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ -#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ -#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ -#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ -#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ -#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ -#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ -#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ -#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ -#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ -#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ -#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ -#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ -#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ -#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ -#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ -#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ -#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ -#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ -#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ -#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ -#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ -#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ -#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ -#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ -#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ -#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ -#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ -#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ -#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ -#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ -#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ -#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ -#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ -#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ -#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ -#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ -#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ -#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ -#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ -#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ -#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ -#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ -#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ -#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ -#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ -#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ -#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ -#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ -#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ -#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */ -#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */ -#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */ -#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ -#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ -#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ -#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 -#define PIO_PE6_IDX 134 -#define PIO_PE7_IDX 135 -#define PIO_PE8_IDX 136 -#define PIO_PE9_IDX 137 -#define PIO_PE10_IDX 138 -#define PIO_PE11_IDX 139 -#define PIO_PE12_IDX 140 -#define PIO_PE13_IDX 141 -#define PIO_PE14_IDX 142 -#define PIO_PE15_IDX 143 -#define PIO_PE16_IDX 144 -#define PIO_PE17_IDX 145 -#define PIO_PE18_IDX 146 -#define PIO_PE19_IDX 147 -#define PIO_PE20_IDX 148 -#define PIO_PE21_IDX 149 -#define PIO_PE22_IDX 150 -#define PIO_PE23_IDX 151 -#define PIO_PE24_IDX 152 -#define PIO_PE25_IDX 153 -#define PIO_PE26_IDX 154 -#define PIO_PE27_IDX 155 -#define PIO_PE28_IDX 156 -#define PIO_PE29_IDX 157 -#define PIO_PE30_IDX 158 -#define PIO_PE31_IDX 159 -#define PIO_PF0_IDX 160 -#define PIO_PF1_IDX 161 -#define PIO_PF2_IDX 162 -#define PIO_PF3_IDX 163 -#define PIO_PF4_IDX 164 -#define PIO_PF5_IDX 165 - -#endif /* _SAM3X4G_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4h.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4h.h deleted file mode 100644 index e74cd395e..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4h.h +++ /dev/null @@ -1,680 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X4H_PIO_ -#define _SAM3X4H_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ -#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ -#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ -#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ -#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ -#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ -#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ -#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ -#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ -#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ -#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ -#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ -#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ -#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ -#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ -#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ -#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ -#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ -#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ -#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ -#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ -#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ -#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ -#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ -#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ -#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ -#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */ -#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */ -#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */ -#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */ -#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */ -#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ -#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ -#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ -#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ -#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ -#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ -#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ -#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ -#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ -#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ -#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ -#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ -#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ -#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ -#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ -#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ -#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ -#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ -#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ -#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ -#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ -#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ -#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ -#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ -#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ -#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ -#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ -#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ -#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ -#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ -#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ -#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ -#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ -#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ -#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ -#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ -#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ -#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ -#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ -#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ -#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ -#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ -#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ -#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ -#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ -#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ -#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ -#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ -#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ -#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ -#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ -#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ -#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ -#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ -#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ -#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ -#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ -#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ -#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ -#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ -#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ -#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ -#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ -#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ -#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ -#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ -#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ -#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ -#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ -#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */ -#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */ -#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */ -#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ -#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ -#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ -#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 -#define PIO_PE6_IDX 134 -#define PIO_PE7_IDX 135 -#define PIO_PE8_IDX 136 -#define PIO_PE9_IDX 137 -#define PIO_PE10_IDX 138 -#define PIO_PE11_IDX 139 -#define PIO_PE12_IDX 140 -#define PIO_PE13_IDX 141 -#define PIO_PE14_IDX 142 -#define PIO_PE15_IDX 143 -#define PIO_PE16_IDX 144 -#define PIO_PE17_IDX 145 -#define PIO_PE18_IDX 146 -#define PIO_PE19_IDX 147 -#define PIO_PE20_IDX 148 -#define PIO_PE21_IDX 149 -#define PIO_PE22_IDX 150 -#define PIO_PE23_IDX 151 -#define PIO_PE24_IDX 152 -#define PIO_PE25_IDX 153 -#define PIO_PE26_IDX 154 -#define PIO_PE27_IDX 155 -#define PIO_PE28_IDX 156 -#define PIO_PE29_IDX 157 -#define PIO_PE30_IDX 158 -#define PIO_PE31_IDX 159 -#define PIO_PF0_IDX 160 -#define PIO_PF1_IDX 161 -#define PIO_PF2_IDX 162 -#define PIO_PF3_IDX 163 -#define PIO_PF4_IDX 164 -#define PIO_PF5_IDX 165 - -#endif /* _SAM3X4H_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8g.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8g.h deleted file mode 100644 index fb73dfa80..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8g.h +++ /dev/null @@ -1,680 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X8G_PIO_ -#define _SAM3X8G_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ -#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ -#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ -#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ -#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ -#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ -#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ -#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ -#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ -#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ -#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ -#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ -#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ -#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ -#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ -#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ -#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ -#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ -#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ -#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ -#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ -#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ -#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ -#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ -#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ -#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ -#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */ -#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */ -#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */ -#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */ -#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */ -#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ -#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ -#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ -#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ -#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ -#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ -#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ -#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ -#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ -#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ -#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ -#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ -#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ -#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ -#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ -#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ -#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ -#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ -#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ -#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ -#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ -#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ -#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ -#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ -#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ -#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ -#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ -#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ -#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ -#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ -#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ -#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ -#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ -#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ -#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ -#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ -#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ -#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ -#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ -#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ -#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ -#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ -#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ -#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ -#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ -#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ -#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ -#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ -#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ -#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ -#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ -#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ -#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ -#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ -#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ -#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ -#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ -#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ -#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ -#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ -#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ -#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ -#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ -#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ -#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ -#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ -#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ -#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ -#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ -#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ -#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ -#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ -#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ -#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ -#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ -#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ -#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ -#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ -#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ -#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ -#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ -#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ -#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ -#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ -#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ -#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ -#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ -#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ -#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ -#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ -#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ -/* ========== Pio definition for EMAC peripheral ========== */ -#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ -#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ -#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ -#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ -#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ -#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ -#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ -#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ -#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ -#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ -#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ -#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ -#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ -#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ -#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ -#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ -#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ -#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ -#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ -#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ -#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ -#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ -#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ -#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ -#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ -#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ -#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ -#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ -#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ -#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ -#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ -#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ -#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ -#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ -#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ -#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ -#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ -#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ -#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ -#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ -#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ -#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ -#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ -#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ -#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */ -#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */ -#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */ -#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ -#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ -#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ -#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ -#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ -#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ -#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ -#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ -#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ -/* ========== Pio definition for UOTGHS peripheral ========== */ -#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ -#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 -#define PIO_PB16_IDX 48 -#define PIO_PB17_IDX 49 -#define PIO_PB18_IDX 50 -#define PIO_PB19_IDX 51 -#define PIO_PB20_IDX 52 -#define PIO_PB21_IDX 53 -#define PIO_PB22_IDX 54 -#define PIO_PB23_IDX 55 -#define PIO_PB24_IDX 56 -#define PIO_PB25_IDX 57 -#define PIO_PB26_IDX 58 -#define PIO_PB27_IDX 59 -#define PIO_PB28_IDX 60 -#define PIO_PB29_IDX 61 -#define PIO_PB30_IDX 62 -#define PIO_PB31_IDX 63 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 -#define PIO_PE6_IDX 134 -#define PIO_PE7_IDX 135 -#define PIO_PE8_IDX 136 -#define PIO_PE9_IDX 137 -#define PIO_PE10_IDX 138 -#define PIO_PE11_IDX 139 -#define PIO_PE12_IDX 140 -#define PIO_PE13_IDX 141 -#define PIO_PE14_IDX 142 -#define PIO_PE15_IDX 143 -#define PIO_PE16_IDX 144 -#define PIO_PE17_IDX 145 -#define PIO_PE18_IDX 146 -#define PIO_PE19_IDX 147 -#define PIO_PE20_IDX 148 -#define PIO_PE21_IDX 149 -#define PIO_PE22_IDX 150 -#define PIO_PE23_IDX 151 -#define PIO_PE24_IDX 152 -#define PIO_PE25_IDX 153 -#define PIO_PE26_IDX 154 -#define PIO_PE27_IDX 155 -#define PIO_PE28_IDX 156 -#define PIO_PE29_IDX 157 -#define PIO_PE30_IDX 158 -#define PIO_PE31_IDX 159 -#define PIO_PF0_IDX 160 -#define PIO_PF1_IDX 161 -#define PIO_PF2_IDX 162 -#define PIO_PF3_IDX 163 -#define PIO_PF4_IDX 164 -#define PIO_PF5_IDX 165 - -#endif /* _SAM3X8G_PIO_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2c.h deleted file mode 100644 index 707cbb403..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2c.h +++ /dev/null @@ -1,408 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2C_ -#define _SAM3X2C_ - -/** \addtogroup SAM3X2C_definitions SAM3X2C definitions - This file defines all structures and symbols for SAM3X2C: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2C_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X2C specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X2C Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X2C Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X2C Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X2C Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X2C Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X2C Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X2C Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X2C Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X2C Universal Asynchronous Receiver Transceiver (UART) */ - PIOA_IRQn = 11, /**< 11 SAM3X2C Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X2C Parallel I/O Controller B (PIOB) */ - USART0_IRQn = 17, /**< 17 SAM3X2C USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X2C USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X2C USART 2 (USART2) */ - HSMCI_IRQn = 21, /**< 21 SAM3X2C Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X2C Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X2C Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X2C Serial Peripheral Interface (SPI0) */ - SSC_IRQn = 26, /**< 26 SAM3X2C Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X2C Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X2C Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X2C Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X2C Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X2C Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X2C Timer Counter 5 (TC5) */ - PWM_IRQn = 36, /**< 36 SAM3X2C Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X2C ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X2C DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X2C DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X2C USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X2C True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X2C Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X2C CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X2C CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X2C core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X2C does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X2C uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X2C */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2C_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2C_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2C_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2C_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2C_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x2c.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x10000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (256u) -#define IFLASH1_SIZE (0x10000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (256u) -#define IRAM0_SIZE (0x4000u) -#define IRAM1_SIZE (0x4000u) -#define IFLASH_SIZE (0x20000u) -#define IRAM_SIZE (0x8000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X2C */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X2C_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2e.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2e.h deleted file mode 100644 index 127413cfa..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2e.h +++ /dev/null @@ -1,441 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2E_ -#define _SAM3X2E_ - -/** \addtogroup SAM3X2E_definitions SAM3X2E definitions - This file defines all structures and symbols for SAM3X2E: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2E_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X2E specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X2E Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X2E Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X2E Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X2E Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X2E Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X2E Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X2E Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X2E Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X2E Universal Asynchronous Receiver Transceiver (UART) */ - SMC_IRQn = 9, /**< 9 SAM3X2E Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 SAM3X2E Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X2E Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 SAM3X2E Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 14, /**< 14 SAM3X2E Parallel I/O Controller D (PIOD) */ - USART0_IRQn = 17, /**< 17 SAM3X2E USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X2E USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X2E USART 2 (USART2) */ - USART3_IRQn = 20, /**< 20 SAM3X2E USART 3 (USART3) */ - HSMCI_IRQn = 21, /**< 21 SAM3X2E Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X2E Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X2E Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X2E Serial Peripheral Interface (SPI0) */ - SSC_IRQn = 26, /**< 26 SAM3X2E Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X2E Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X2E Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X2E Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X2E Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X2E Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X2E Timer Counter 5 (TC5) */ - TC6_IRQn = 33, /**< 33 SAM3X2E Timer Counter 6 (TC6) */ - TC7_IRQn = 34, /**< 34 SAM3X2E Timer Counter 7 (TC7) */ - TC8_IRQn = 35, /**< 35 SAM3X2E Timer Counter 8 (TC8) */ - PWM_IRQn = 36, /**< 36 SAM3X2E Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X2E ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X2E DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X2E DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X2E USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X2E True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X2E Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X2E CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X2E CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X2E core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X2E does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X2E uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X2E */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2E_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_smc.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2E_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_tc2.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_usart3.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_smc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_pioc.h" -#include "instance/instance_piod.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2E_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ -#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ -#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2E_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2E_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x2e.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x10000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (256u) -#define IFLASH1_SIZE (0x10000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (256u) -#define IRAM0_SIZE (0x4000u) -#define IRAM1_SIZE (0x4000u) -#define NFCRAM_SIZE (0x1000u) -#define IFLASH_SIZE (0x20000u) -#define IRAM_SIZE (0x8000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X2E */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X2E_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2g.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2g.h deleted file mode 100644 index 345b8e040..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2g.h +++ /dev/null @@ -1,462 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2G_ -#define _SAM3X2G_ - -/** \addtogroup SAM3X2G_definitions SAM3X2G definitions - This file defines all structures and symbols for SAM3X2G: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2G_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X2G specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X2G Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X2G Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X2G Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X2G Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X2G Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X2G Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X2G Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X2G Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X2G Universal Asynchronous Receiver Transceiver (UART) */ - SMC_IRQn = 9, /**< 9 SAM3X2G Static Memory Controller (SMC) */ - SDRAMC_IRQn = 10, /**< 10 SAM3X2G Synchronous Dynamic RAM Controller (SDRAMC) */ - PIOA_IRQn = 11, /**< 11 SAM3X2G Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X2G Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 SAM3X2G Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 14, /**< 14 SAM3X2G Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 15, /**< 15 SAM3X2G Parallel I/O Controller E (PIOE) */ - PIOF_IRQn = 16, /**< 16 SAM3X2G Parallel I/O Controller F (PIOF) */ - USART0_IRQn = 17, /**< 17 SAM3X2G USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X2G USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X2G USART 2 (USART2) */ - USART3_IRQn = 20, /**< 20 SAM3X2G USART 3 (USART3) */ - HSMCI_IRQn = 21, /**< 21 SAM3X2G Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X2G Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X2G Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X2G Serial Peripheral Interface (SPI0) */ - SPI1_IRQn = 25, /**< 25 SAM3X2G Serial Peripheral Interface (SPI1) */ - SSC_IRQn = 26, /**< 26 SAM3X2G Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X2G Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X2G Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X2G Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X2G Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X2G Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X2G Timer Counter 5 (TC5) */ - TC6_IRQn = 33, /**< 33 SAM3X2G Timer Counter 6 (TC6) */ - TC7_IRQn = 34, /**< 34 SAM3X2G Timer Counter 7 (TC7) */ - TC8_IRQn = 35, /**< 35 SAM3X2G Timer Counter 8 (TC8) */ - PWM_IRQn = 36, /**< 36 SAM3X2G Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X2G ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X2G DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X2G DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X2G USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X2G True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X2G Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X2G CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X2G CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X2G core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X2G does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X2G uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X2G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2G_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_sdramc.h" -#include "component/component_smc.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2G_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_spi1.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_tc2.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_usart3.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_smc.h" -#include "instance/instance_sdramc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_pioc.h" -#include "instance/instance_piod.h" -#include "instance/instance_pioe.h" -#include "instance/instance_piof.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2G_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ -#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ -#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2G_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2G_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x2g.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x10000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (256u) -#define IFLASH1_SIZE (0x10000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (256u) -#define IRAM0_SIZE (0x4000u) -#define IRAM1_SIZE (0x4000u) -#define NFCRAM_SIZE (0x1000u) -#define IFLASH_SIZE (0x20000u) -#define IRAM_SIZE (0x8000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X2G */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X2G_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2h.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2h.h deleted file mode 100644 index 55c09276e..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x2h.h +++ /dev/null @@ -1,462 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X2H_ -#define _SAM3X2H_ - -/** \addtogroup SAM3X2H_definitions SAM3X2H definitions - This file defines all structures and symbols for SAM3X2H: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2H_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X2H specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X2H Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X2H Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X2H Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X2H Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X2H Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X2H Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X2H Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X2H Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X2H Universal Asynchronous Receiver Transceiver (UART) */ - SMC_IRQn = 9, /**< 9 SAM3X2H Static Memory Controller (SMC) */ - SDRAMC_IRQn = 10, /**< 10 SAM3X2H Synchronous Dynamic RAM Controller (SDRAMC) */ - PIOA_IRQn = 11, /**< 11 SAM3X2H Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X2H Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 SAM3X2H Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 14, /**< 14 SAM3X2H Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 15, /**< 15 SAM3X2H Parallel I/O Controller E (PIOE) */ - PIOF_IRQn = 16, /**< 16 SAM3X2H Parallel I/O Controller F (PIOF) */ - USART0_IRQn = 17, /**< 17 SAM3X2H USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X2H USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X2H USART 2 (USART2) */ - USART3_IRQn = 20, /**< 20 SAM3X2H USART 3 (USART3) */ - HSMCI_IRQn = 21, /**< 21 SAM3X2H Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X2H Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X2H Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X2H Serial Peripheral Interface (SPI0) */ - SPI1_IRQn = 25, /**< 25 SAM3X2H Serial Peripheral Interface (SPI1) */ - SSC_IRQn = 26, /**< 26 SAM3X2H Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X2H Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X2H Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X2H Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X2H Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X2H Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X2H Timer Counter 5 (TC5) */ - TC6_IRQn = 33, /**< 33 SAM3X2H Timer Counter 6 (TC6) */ - TC7_IRQn = 34, /**< 34 SAM3X2H Timer Counter 7 (TC7) */ - TC8_IRQn = 35, /**< 35 SAM3X2H Timer Counter 8 (TC8) */ - PWM_IRQn = 36, /**< 36 SAM3X2H Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X2H ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X2H DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X2H DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X2H USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X2H True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X2H Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X2H CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X2H CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X2H core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X2H does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X2H uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X2H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2H_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_sdramc.h" -#include "component/component_smc.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2H_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_spi1.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_tc2.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_usart3.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_smc.h" -#include "instance/instance_sdramc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_pioc.h" -#include "instance/instance_piod.h" -#include "instance/instance_pioe.h" -#include "instance/instance_piof.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2H_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ -#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ -#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2H_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X2H_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x2h.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x10000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (256u) -#define IFLASH1_SIZE (0x10000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (256u) -#define IRAM0_SIZE (0x4000u) -#define IRAM1_SIZE (0x4000u) -#define NFCRAM_SIZE (0x1000u) -#define IFLASH_SIZE (0x20000u) -#define IRAM_SIZE (0x8000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X2H */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X2H_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4g.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4g.h deleted file mode 100644 index 0c9660eba..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4g.h +++ /dev/null @@ -1,462 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X4G_ -#define _SAM3X4G_ - -/** \addtogroup SAM3X4G_definitions SAM3X4G definitions - This file defines all structures and symbols for SAM3X4G: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4G_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X4G specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X4G Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X4G Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X4G Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X4G Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X4G Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X4G Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X4G Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X4G Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X4G Universal Asynchronous Receiver Transceiver (UART) */ - SMC_IRQn = 9, /**< 9 SAM3X4G Static Memory Controller (SMC) */ - SDRAMC_IRQn = 10, /**< 10 SAM3X4G Synchronous Dynamic RAM Controller (SDRAMC) */ - PIOA_IRQn = 11, /**< 11 SAM3X4G Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X4G Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 SAM3X4G Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 14, /**< 14 SAM3X4G Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 15, /**< 15 SAM3X4G Parallel I/O Controller E (PIOE) */ - PIOF_IRQn = 16, /**< 16 SAM3X4G Parallel I/O Controller F (PIOF) */ - USART0_IRQn = 17, /**< 17 SAM3X4G USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X4G USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X4G USART 2 (USART2) */ - USART3_IRQn = 20, /**< 20 SAM3X4G USART 3 (USART3) */ - HSMCI_IRQn = 21, /**< 21 SAM3X4G Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X4G Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X4G Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X4G Serial Peripheral Interface (SPI0) */ - SPI1_IRQn = 25, /**< 25 SAM3X4G Serial Peripheral Interface (SPI1) */ - SSC_IRQn = 26, /**< 26 SAM3X4G Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X4G Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X4G Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X4G Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X4G Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X4G Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X4G Timer Counter 5 (TC5) */ - TC6_IRQn = 33, /**< 33 SAM3X4G Timer Counter 6 (TC6) */ - TC7_IRQn = 34, /**< 34 SAM3X4G Timer Counter 7 (TC7) */ - TC8_IRQn = 35, /**< 35 SAM3X4G Timer Counter 8 (TC8) */ - PWM_IRQn = 36, /**< 36 SAM3X4G Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X4G ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X4G DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X4G DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X4G USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X4G True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X4G Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X4G CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X4G CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X4G core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X4G does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X4G uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4G_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_sdramc.h" -#include "component/component_smc.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4G_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_spi1.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_tc2.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_usart3.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_smc.h" -#include "instance/instance_sdramc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_pioc.h" -#include "instance/instance_piod.h" -#include "instance/instance_pioe.h" -#include "instance/instance_piof.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4G_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ -#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ -#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4G_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4G_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x4g.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x20000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (512u) -#define IFLASH1_SIZE (0x20000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (512u) -#define IRAM0_SIZE (0x8000u) -#define IRAM1_SIZE (0x8000u) -#define NFCRAM_SIZE (0x1000u) -#define IFLASH_SIZE (0x40000u) -#define IRAM_SIZE (0x10000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X4G */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X4G_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4h.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4h.h deleted file mode 100644 index dd0657b22..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4h.h +++ /dev/null @@ -1,462 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X4H_ -#define _SAM3X4H_ - -/** \addtogroup SAM3X4H_definitions SAM3X4H definitions - This file defines all structures and symbols for SAM3X4H: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4H_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X4H specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X4H Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X4H Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X4H Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X4H Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X4H Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X4H Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X4H Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X4H Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X4H Universal Asynchronous Receiver Transceiver (UART) */ - SMC_IRQn = 9, /**< 9 SAM3X4H Static Memory Controller (SMC) */ - SDRAMC_IRQn = 10, /**< 10 SAM3X4H Synchronous Dynamic RAM Controller (SDRAMC) */ - PIOA_IRQn = 11, /**< 11 SAM3X4H Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X4H Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 SAM3X4H Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 14, /**< 14 SAM3X4H Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 15, /**< 15 SAM3X4H Parallel I/O Controller E (PIOE) */ - PIOF_IRQn = 16, /**< 16 SAM3X4H Parallel I/O Controller F (PIOF) */ - USART0_IRQn = 17, /**< 17 SAM3X4H USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X4H USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X4H USART 2 (USART2) */ - USART3_IRQn = 20, /**< 20 SAM3X4H USART 3 (USART3) */ - HSMCI_IRQn = 21, /**< 21 SAM3X4H Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X4H Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X4H Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X4H Serial Peripheral Interface (SPI0) */ - SPI1_IRQn = 25, /**< 25 SAM3X4H Serial Peripheral Interface (SPI1) */ - SSC_IRQn = 26, /**< 26 SAM3X4H Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X4H Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X4H Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X4H Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X4H Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X4H Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X4H Timer Counter 5 (TC5) */ - TC6_IRQn = 33, /**< 33 SAM3X4H Timer Counter 6 (TC6) */ - TC7_IRQn = 34, /**< 34 SAM3X4H Timer Counter 7 (TC7) */ - TC8_IRQn = 35, /**< 35 SAM3X4H Timer Counter 8 (TC8) */ - PWM_IRQn = 36, /**< 36 SAM3X4H Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X4H ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X4H DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X4H DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X4H USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X4H True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X4H Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X4H CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X4H CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X4H core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X4H does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X4H uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4H_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_sdramc.h" -#include "component/component_smc.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4H_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_spi1.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_tc2.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_usart3.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_smc.h" -#include "instance/instance_sdramc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_pioc.h" -#include "instance/instance_piod.h" -#include "instance/instance_pioe.h" -#include "instance/instance_piof.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4H_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ -#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ -#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4H_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ -/** \addtogroup SAM3X4H_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x4h.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x20000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (512u) -#define IFLASH1_SIZE (0x20000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (512u) -#define IRAM0_SIZE (0x8000u) -#define IRAM1_SIZE (0x8000u) -#define NFCRAM_SIZE (0x1000u) -#define IFLASH_SIZE (0x40000u) -#define IRAM_SIZE (0x10000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X4H */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X4H_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8g.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8g.h deleted file mode 100644 index 9a76fa84a..000000000 --- a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8g.h +++ /dev/null @@ -1,462 +0,0 @@ -/* ---------------------------------------------------------------------------- - * SAM Software Package License - * ---------------------------------------------------------------------------- - * Copyright (c) 2011, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _SAM3X8G_ -#define _SAM3X8G_ - -/** \addtogroup SAM3X8G_definitions SAM3X8G definitions - This file defines all structures and symbols for SAM3X8G: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X8G_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** SAM3X8G specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM3X8G Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM3X8G Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM3X8G Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM3X8G Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM3X8G Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM3X8G Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 SAM3X8G Enhanced Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 SAM3X8G Enhanced Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 SAM3X8G Universal Asynchronous Receiver Transceiver (UART) */ - SMC_IRQn = 9, /**< 9 SAM3X8G Static Memory Controller (SMC) */ - SDRAMC_IRQn = 10, /**< 10 SAM3X8G Synchronous Dynamic RAM Controller (SDRAMC) */ - PIOA_IRQn = 11, /**< 11 SAM3X8G Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAM3X8G Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 SAM3X8G Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 14, /**< 14 SAM3X8G Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 15, /**< 15 SAM3X8G Parallel I/O Controller E (PIOE) */ - PIOF_IRQn = 16, /**< 16 SAM3X8G Parallel I/O Controller F (PIOF) */ - USART0_IRQn = 17, /**< 17 SAM3X8G USART 0 (USART0) */ - USART1_IRQn = 18, /**< 18 SAM3X8G USART 1 (USART1) */ - USART2_IRQn = 19, /**< 19 SAM3X8G USART 2 (USART2) */ - USART3_IRQn = 20, /**< 20 SAM3X8G USART 3 (USART3) */ - HSMCI_IRQn = 21, /**< 21 SAM3X8G Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 22, /**< 22 SAM3X8G Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 23, /**< 23 SAM3X8G Two-Wire Interface 1 (TWI1) */ - SPI0_IRQn = 24, /**< 24 SAM3X8G Serial Peripheral Interface (SPI0) */ - SPI1_IRQn = 25, /**< 25 SAM3X8G Serial Peripheral Interface (SPI1) */ - SSC_IRQn = 26, /**< 26 SAM3X8G Synchronous Serial Controller (SSC) */ - TC0_IRQn = 27, /**< 27 SAM3X8G Timer Counter 0 (TC0) */ - TC1_IRQn = 28, /**< 28 SAM3X8G Timer Counter 1 (TC1) */ - TC2_IRQn = 29, /**< 29 SAM3X8G Timer Counter 2 (TC2) */ - TC3_IRQn = 30, /**< 30 SAM3X8G Timer Counter 3 (TC3) */ - TC4_IRQn = 31, /**< 31 SAM3X8G Timer Counter 4 (TC4) */ - TC5_IRQn = 32, /**< 32 SAM3X8G Timer Counter 5 (TC5) */ - TC6_IRQn = 33, /**< 33 SAM3X8G Timer Counter 6 (TC6) */ - TC7_IRQn = 34, /**< 34 SAM3X8G Timer Counter 7 (TC7) */ - TC8_IRQn = 35, /**< 35 SAM3X8G Timer Counter 8 (TC8) */ - PWM_IRQn = 36, /**< 36 SAM3X8G Pulse Width Modulation Controller (PWM) */ - ADC_IRQn = 37, /**< 37 SAM3X8G ADC Controller (ADC) */ - DACC_IRQn = 38, /**< 38 SAM3X8G DAC Controller (DACC) */ - DMAC_IRQn = 39, /**< 39 SAM3X8G DMA Controller (DMAC) */ - UOTGHS_IRQn = 40, /**< 40 SAM3X8G USB OTG High Speed (UOTGHS) */ - TRNG_IRQn = 41, /**< 41 SAM3X8G True Random Number Generator (TRNG) */ - EMAC_IRQn = 42, /**< 42 SAM3X8G Ethernet MAC (EMAC) */ - CAN0_IRQn = 43, /**< 43 SAM3X8G CAN Controller 0 (CAN0) */ - CAN1_IRQn = 44 /**< 44 SAM3X8G CAN Controller 1 (CAN1) */ -} IRQn_Type; - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ - -#define __CM3_REV 0x0200 /**< SAM3X8G core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAM3X8G does provide a MPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM3X8G uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X8G_api Peripheral Software API */ -/*@{*/ - -#include "component/component_adc.h" -#include "component/component_can.h" -#include "component/component_chipid.h" -#include "component/component_dacc.h" -#include "component/component_dmac.h" -#include "component/component_efc.h" -#include "component/component_emac.h" -#include "component/component_gpbr.h" -#include "component/component_hsmci.h" -#include "component/component_matrix.h" -#include "component/component_pdc.h" -#include "component/component_pio.h" -#include "component/component_pmc.h" -#include "component/component_pwm.h" -#include "component/component_rstc.h" -#include "component/component_rtc.h" -#include "component/component_rtt.h" -#include "component/component_sdramc.h" -#include "component/component_smc.h" -#include "component/component_spi.h" -#include "component/component_ssc.h" -#include "component/component_supc.h" -#include "component/component_tc.h" -#include "component/component_trng.h" -#include "component/component_twi.h" -#include "component/component_uart.h" -#include "component/component_uotghs.h" -#include "component/component_usart.h" -#include "component/component_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X8G_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/instance_hsmci.h" -#include "instance/instance_ssc.h" -#include "instance/instance_spi0.h" -#include "instance/instance_spi1.h" -#include "instance/instance_tc0.h" -#include "instance/instance_tc1.h" -#include "instance/instance_tc2.h" -#include "instance/instance_twi0.h" -#include "instance/instance_twi1.h" -#include "instance/instance_pwm.h" -#include "instance/instance_usart0.h" -#include "instance/instance_usart1.h" -#include "instance/instance_usart2.h" -#include "instance/instance_usart3.h" -#include "instance/instance_uotghs.h" -#include "instance/instance_emac.h" -#include "instance/instance_can0.h" -#include "instance/instance_can1.h" -#include "instance/instance_trng.h" -#include "instance/instance_adc.h" -#include "instance/instance_dmac.h" -#include "instance/instance_dacc.h" -#include "instance/instance_smc.h" -#include "instance/instance_sdramc.h" -#include "instance/instance_matrix.h" -#include "instance/instance_pmc.h" -#include "instance/instance_uart.h" -#include "instance/instance_chipid.h" -#include "instance/instance_efc0.h" -#include "instance/instance_efc1.h" -#include "instance/instance_pioa.h" -#include "instance/instance_piob.h" -#include "instance/instance_pioc.h" -#include "instance/instance_piod.h" -#include "instance/instance_pioe.h" -#include "instance/instance_piof.h" -#include "instance/instance_rstc.h" -#include "instance/instance_supc.h" -#include "instance/instance_rtt.h" -#include "instance/instance_wdt.h" -#include "instance/instance_rtc.h" -#include "instance/instance_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X8G_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */ -#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ -#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */ -#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ -#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ -#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ -#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ -#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ -#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ -#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ -#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ -#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ -#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ -#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ -#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ -#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ -#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ -#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X8G_base Peripheral Base Address Definitions */ -/*@{*/ - -#ifdef __ASSEMBLY__ -#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#else -#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ -#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */ -#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ -#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ -#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ -#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ -#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ -#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ -#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ -#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ -#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ -#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ -#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ -#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ -#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */ -#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ -#endif /* __ASSEMBLY__ */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ -/** \addtogroup SAM3X8G_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/pio_sam3x8g.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ - -#define IFLASH0_SIZE (0x40000u) -#define IFLASH0_PAGE_SIZE (256u) -#define IFLASH0_LOCK_REGION_SIZE (16384u) -#define IFLASH0_NB_OF_PAGES (1024u) -#define IFLASH1_SIZE (0x40000u) -#define IFLASH1_PAGE_SIZE (256u) -#define IFLASH1_LOCK_REGION_SIZE (16384u) -#define IFLASH1_NB_OF_PAGES (1024u) -#define IRAM0_SIZE (0x10000u) -#define IRAM1_SIZE (0x8000u) -#define NFCRAM_SIZE (0x1000u) -#define IFLASH_SIZE (0x80000u) -#define IRAM_SIZE (0x18000u) - -#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ -#if defined IFLASH0_SIZE -#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ -#endif -#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ -#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ -#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ -#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ -#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ -#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ -#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ -#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ -#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM3X8G */ -/* ************************************************************************** */ - -/* Device characteristics */ - -#define CHIP_FREQ_SLCK_RC_MIN (20000U) -#define CHIP_FREQ_SLCK_RC (32000U) -#define CHIP_FREQ_SLCK_RC_MAX (44000U) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U) -#define CHIP_FREQ_CPU_MAX (84000000U) -#define CHIP_FLASH_WAIT_STATE (3U) - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM3X8G_ */ diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c index f588b6e01..3afa1c96c 100644 --- a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c +++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c @@ -15,11 +15,6 @@ #include "../exceptions.h" #include "sam3.h" -/* Stack Configuration */ -#define STACK_SIZE 0x900 /** Stack size (in DWords) */ -__attribute__ ((aligned(8), section(".stack"))) -uint32_t pdwStack[STACK_SIZE]; - /* Initialize segments */ extern uint32_t _sfixed; extern uint32_t _efixed; @@ -28,6 +23,8 @@ extern uint32_t _srelocate; extern uint32_t _erelocate; extern uint32_t _szero; extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; /** \cond DOXYGEN_SHOULD_SKIP_THIS */ int main(void); @@ -40,7 +37,7 @@ __attribute__ ((section(".vectors"))) IntFunc exception_table[] = { /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc) (&pdwStack[STACK_SIZE - 1]), + (IntFunc) (&_estack), Reset_Handler, NMI_Handler, diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c index d92dd9c5a..27186e512 100644 --- a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c +++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c @@ -28,7 +28,7 @@ extern "C" { /* Clock settings (84MHz) */ #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8)) -#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \ +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ | CKGR_PLLAR_MULA(0x6) \ | CKGR_PLLAR_PLLACOUNT(0x3f) \ | CKGR_PLLAR_DIVA(0x1)) @@ -96,35 +96,6 @@ void SystemInit(void) SystemCoreClock = CHIP_FREQ_CPU_MAX; } -/** - * Initialize the flash and watchdog setting . - */ -void set_flash_and_watchdog(void) -{ - /* Set FWS for Embedded Flash Access according operating frequency*/ - if(SystemCoreClock < SYS_FREQ_FWS_0){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); - }else if(SystemCoreClock < SYS_FREQ_FWS_1){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(1); - EFC1->EEFC_FMR = EEFC_FMR_FWS(1); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(2); - EFC1->EEFC_FMR = EEFC_FMR_FWS(2); - }else if(SystemCoreClock < SYS_FREQ_FWS_2){ - EFC0->EEFC_FMR = EEFC_FMR_FWS(3); - EFC1->EEFC_FMR = EEFC_FMR_FWS(3); - }else{ - EFC0->EEFC_FMR = EEFC_FMR_FWS(4); - EFC1->EEFC_FMR = EEFC_FMR_FWS(4); - } - -#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT - /*Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif -} - void SystemCoreClockUpdate(void) { /* Determine clock frequency according to clock register values */ @@ -143,12 +114,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -164,12 +135,12 @@ void SystemCoreClockUpdate(void) SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4MHz: + case CKGR_MOR_MOSCRCF_4_MHz: break; - case CKGR_MOR_MOSCRCF_8MHz: + case CKGR_MOR_MOSCRCF_8_MHz: SystemCoreClock *= 2U; break; - case CKGR_MOR_MOSCRCF_12MHz: + case CKGR_MOR_MOSCRCF_12_MHz: SystemCoreClock *= 3U; break; default: @@ -195,6 +166,35 @@ void SystemCoreClockUpdate(void) } } +/** + * Initialize flash and watchdog. + */ +void system_init_flash_and_watchdog(uint32_t dw_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (dw_clk < SYS_FREQ_FWS_0) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); + } else if (dw_clk < SYS_FREQ_FWS_1) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(1); + EFC1->EEFC_FMR = EEFC_FMR_FWS(1); + } else if (dw_clk < SYS_FREQ_FWS_2) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(2); + EFC1->EEFC_FMR = EEFC_FMR_FWS(2); + } else if (dw_clk < SYS_FREQ_FWS_3) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(3); + EFC1->EEFC_FMR = EEFC_FMR_FWS(3); + } else { + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + } + +#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} + /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus diff --git a/hardware/sam/system/libsam/include/adc.h b/hardware/sam/system/libsam/include/adc.h index f1cd4f136..2d189b7ee 100644 --- a/hardware/sam/system/libsam/include/adc.h +++ b/hardware/sam/system/libsam/include/adc.h @@ -38,17 +38,11 @@ * *******************************************************************************/ - - #ifndef ADC_H_INCLUDED #define ADC_H_INCLUDED #include "../chip.h" -#if SAM3U -#define ADC_12B -#endif - #define ADC_FREQ_MAX 20000000 #define ADC_FREQ_MIN 1000000 @@ -56,30 +50,24 @@ #define ADC_STARTUP_FAST 12 /* Definitions for ADC resolution */ -#if SAM3S || SAM3XA typedef enum _adc_resolution_t { +#if SAM3N || SAM3U + ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */ +#endif /* SAM3N || SAM3U */ ADC_10_BITS = ADC_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */ - ADC_12_BITS = ADC_MR_LOWRES_BITS_12 /* ADC 12-bit resolution */ +#if SAM3S || SAM3XA + ADC_12_BITS = ADC_MR_LOWRES_BITS_12, /* ADC 12-bit resolution */ +#endif /* SAM3S || SAM3XA */ + ADC_NONE } adc_resolution_t; -#elif SAM3N -typedef enum _adc_resolution_t { - ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */ - ADC_10_BITS = ADC_MR_LOWRES_BITS_10 /* ADC 10-bit resolution */ -} adc_resolution_t; -#elif SAM3U -#ifdef ADC_12B -typedef enum _adc_resolution_t { - ADC_10_BITS = ADC12B_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */ - ADC_12_BITS = ADC12B_MR_LOWRES_BITS_12 /* ADC 12-bit resolution */ -} adc_resolution_t; -#else -typedef enum _adc_resolution_t { - ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */ - ADC_10_BITS = ADC_MR_LOWRES_BITS_10 /* ADC 10-bit resolution */ -} adc_resolution_t; -#endif -#endif +#if SAM3U +typedef enum _adc12_resolution_t { + ADC12_10_BITS = ADC12B_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */ + ADC12_12_BITS = ADC12B_MR_LOWRES_BITS_12 /* ADC 12-bit resolution */ +} adc12_resolution_t; +#endif /* SAM3U */ + /* Definitions for ADC trigger */ typedef enum _adc_trigger_t { ADC_TRIG_SW = ADC_MR_TRGEN_DIS, /* Starting a conversion is only possible by software. */ @@ -93,7 +81,6 @@ typedef enum _adc_trigger_t { #endif } adc_trigger_t; -#if SAM3S || SAM3N || SAM3XA /* Definitions for ADC channel number */ typedef enum _adc_channel_num_t { ADC_CHANNEL_0 = 0, @@ -104,6 +91,7 @@ typedef enum _adc_channel_num_t { ADC_CHANNEL_5 = 5, ADC_CHANNEL_6 = 6, ADC_CHANNEL_7 = 7, +#if SAM3S || SAM3N || SAM3XA ADC_CHANNEL_8 = 8, ADC_CHANNEL_9 = 9, ADC_CHANNEL_10 = 10, @@ -112,920 +100,37 @@ typedef enum _adc_channel_num_t { ADC_CHANNEL_13 = 13, ADC_CHANNEL_14 = 14, ADC_TEMPERATURE_SENSOR = 15, - ADC_ALL_CHANNEL -} adc_channel_num_t; + ADC_ALL_CHANNEL = 0xffff #elif SAM3U -/* Definitions for ADC channel number */ -typedef enum _adc_channel_num_t { - ADC_CHANNEL_0 = 0, - ADC_CHANNEL_1 = 1, - ADC_CHANNEL_2 = 2, - ADC_CHANNEL_3 = 3, - ADC_CHANNEL_4 = 4, - ADC_CHANNEL_5 = 5, - ADC_CHANNEL_6 = 6, - ADC_CHANNEL_7 = 7, - ADC_ALL_CHANNEL + ADC_ALL_CHANNEL = 0xff +#endif /* SAM3U */ } adc_channel_num_t; -#endif -typedef enum{ +typedef enum _adc_gainvalue_t { ADC_GAINVALUE_0 = 0, ADC_GAINVALUE_1 = 1, ADC_GAINVALUE_2 = 2, ADC_GAINVALUE_3 = 3 -}adc_gainvalue_t; +} adc_gainvalue_t ; #if SAM3S || SAM3XA -typedef enum{ +typedef enum { ADC_SETTLING_TIME_0 = ADC_MR_SETTLING_AST3, ADC_SETTLING_TIME_1 = ADC_MR_SETTLING_AST5, ADC_SETTLING_TIME_2 = ADC_MR_SETTLING_AST9, ADC_SETTLING_TIME_3 = ADC_MR_SETTLING_AST17 }adc_settling_time_t; #endif -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond #if SAM3S || SAM3N || SAM3XA -/** - * \brief Initializes the given ADC with the specified ADC clock and startup time. - * - * \param p_adc Pointer to an ADC instance. - * \param dw_mck Main clock of the device (value in Hz). - * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). - * \param uc_startup ADC start up time. Please refer to the product datasheet for details. - * - * \retval 0 The initialization operation succeeds. - * \retval others The initialization operation fails. - */ -extern uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint8_t uc_startup); + +#include "adc_sam3snxa.h" + +#elif SAM3U + +#include "adc10_sam3u.h" +#include "adc12_sam3u.h" #endif - #if SAM3S || SAM3N || SAM3XA -/** - * \brief Configures conversion resolution. - * - * \param p_adc Pointer to an ADC instance. - * \param resolution ADC resolution. - * - */ -extern void adc_set_resolution(Adc *p_adc, adc_resolution_t resolution); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Configures conversion trigger and free run mode. - * - * \param p_adc Pointer to an ADC instance. - * \param trigger Conversion trigger. - * \param uc_freerun ADC_MR_FREERUN_ON enables freerun mode - * ADC_MR_FREERUN_OFF disables freerun mode - * - */ -extern void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger, uint8_t uc_freerun); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Configures ADC power saving mode. - * - * \param p_adc Pointer to an ADC instance. - * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions - * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions - * \param uc_fwup ADC_MR_FWUP_OFF configures sleep mode as uc_sleep setting - * ADC_MR_FWUP_ON keeps voltage reference ON and ADC Core OFF between conversions - * - */ -extern void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_fwup); -/** - * \brief Configures conversion sequence. - * - * \param p_adc Pointer to an ADC instance. - * \param ch_list Channel sequence list. - * \param number Number of channels in the list. - * - */ -extern void adc_configure_sequence(Adc *p_adc, adc_channel_num_t ch_list[], uint8_t uc_num); -#endif - -#if SAM3S || SAM3XA -/** - * \brief Configures ADC timing. - * - * \param p_adc Pointer to an ADC instance. - * \param uc_tracking ADC tracking time = uc_tracking / ADC clock. - * \param uc_settling Analog settling time = (uc_settling + 1) / ADC clock. - * \param uc_transfer Data transfer time = (uc_transfer * 2 + 3) / ADC clock. - * - */ -extern void adc_configure_timing(Adc *p_adc, uint8_t uc_tracking, adc_settling_time_t settling, uint8_t uc_transfer); -#elif SAM3N -/** - * \brief Configures ADC timing. - * - * \param p_adc Pointer to an ADC instance. - * \param uc_tracking ADC tracking time = uc_tracking / ADC clock. - * - */ -extern void adc_configure_timing(Adc *p_adc, uint8_t uc_tracking); - -#endif - -#if SAM3S || SAM3XA -/** - * \brief enable analog change. - * - * note it allows different analog settings for each channel, - * - * \param pAdc Pointer to an Adc instance. - */ -extern void adc_enable_anch( Adc *pAdc ); -#endif - -#if SAM3S || SAM3XA -/** - * \brief disable analog change. - * - * note DIFF0, GAIN0 and OFF0 are used for all channels. - * - * \param pAdc Pointer to an Adc instance. - */ -extern void adc_disable_anch( Adc *pAdc ); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Starts analog-to-digital conversion. - * - * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_start(Adc *p_adc); -/** - * \brief Stop analog-to-digital conversion. - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_stop(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Enables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - */ -extern void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Disables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - */ -extern void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Reads the ADC channel status. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval 1 means the specified channel is enabled. - * 0 means the specified channel is disabled. - */ -extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Reads the ADC result data of the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval ADC data of the specified channel. - */ -extern uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Reads the last ADC result data. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC data. - */ -extern uint32_t adc_get_latest_value(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Enables TAG option so that the number of the last converted channel can be indicated. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_enable_tag(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Disables TAG option. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_disable_tag(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Indicates the last converted channel. - * - * \note If TAG option is NOT enabled before, an incorrect channel number is returned. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval The last converted channel number. - */ -extern adc_channel_num_t adc_get_tag(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Enables conversion sequencer. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_start_sequencer(Adc *p_adc); - -/** - * \brief Disables conversion sequencer. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_stop_sequencer(Adc *p_adc); - -/** - * \brief Configures comparsion mode. - * - * \param p_adc Pointer to an ADC instance. - * \param mode ADC comparsion mode. - * - */ -extern void adc_set_comparison_mode(Adc *p_adc, uint8_t uc_mode); - -/** - * \brief get comparsion mode. - * - * \param p_adc Pointer to an ADC instance. - * \param mode ADC comparsion mode. - * - * \retval compare mode value. - */ -extern uint32_t adc_get_comparison_mode(Adc *p_adc); - -/** - * \brief Configures ADC compare window. - * - * \param p_adc Pointer to an ADC instance. - * \param w_low_threshold Low threshold of compare window. - * \param w_high_threshold High threshold of compare window. - * - */ -extern void adc_set_comparsion_window(Adc *p_adc, uint16_t us_low_threshold, uint16_t us_high_threshold); - -/** - * \brief Configures comparison selected channel. - * - * \param p_adc Pointer to an ADC instance. - * \param channel Comparison selected channel. - * - */ -extern void adc_set_comparison_channel(Adc *p_adc, adc_channel_num_t channel); -#endif - -#if SAM3S || SAM3XA -/** - * \brief Enables differential input for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param channel Channel number. - * - */ -extern void adc_enable_differential_input(Adc *p_adc, adc_channel_num_t channel); - -/** - * \brief Disables differential input for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param channel Channel number. - * - */ -extern void adc_disable_differential_input(Adc *p_adc, adc_channel_num_t channel); - -/** - * \brief Enables analog signal offset for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param channel Channel number. - * - */ -extern void adc_enable_input_offset(Adc *p_adc, adc_channel_num_t channel); - -/** - * \brief Disables analog signal offset for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param channel Channel number. - * - */ -extern void adc_disable_input_offset(Adc *p_adc, adc_channel_num_t channel); - -/** - * \brief Configures input gain for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param channel Channel number. - * \param gain Gain value for the input. - * - */ -extern void adc_set_input_gain(Adc *p_adc, adc_channel_num_t channel, adc_gainvalue_t uc_gain); -#endif - -#if SAM3S8 || SAM3SD8 -/** - * \brief set adc auto calibration mode. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_set_calibmode(Adc *p_adc); -#endif - - #if SAM3S || SAM3N || SAM3XA -/** - * \brief Returns the actual ADC clock. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_mck Main clock of the device (value in Hz). - * - * \retval 0 The actual ADC clock (value in Hz). - */ -extern uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck); -#endif - - #if SAM3S || SAM3N || SAM3XA -/** - * \brief Enables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be enabled. - * - */ -extern void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source); - -/** - * \brief Disables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be disabled. - * - */ -extern void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source); - -/** - * \brief Reads ADC interrupt status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC interrupt status. - */ -extern uint32_t adc_get_interrupt_status(Adc *p_adc); - -/** \brief Read ADC interrupt mask. - * - * \param p_uart pointer to a UART instance. - * - * \return The interrupt mask value. - */ -extern uint32_t adc_get_interrupt_mask(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Reads overrun status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC overrun status. - */ -extern uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch); -#endif - -#if SAM3S || SAM3XA -/** - * \brief Adapts performance versus power consumption. - * - * \note Please refer to ADC Characteristics in the product datasheet for the details. - * - * \param p_adc Pointer to an ADC instance. - * \param ibctl ADC Bias current control. - * - */ -extern void adc_set_bias_current(Adc *p_adc, uint8_t uc_ibctl); -#endif - -#if SAM3S || SAM3XA -/** - * \brief turn on temperature sensor. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_enable_ts(Adc *p_adc); - -/** - * \brief turn off temperature sensor. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_disable_ts(Adc *p_adc); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Enables or disables write protection of ADC registers. - * - * \param p_adc Pointer to an ADC instance. - * \param dw_eanble 1 to eanble, 0 to disable. - */ -extern void adc_set_writeprotect(Adc *p_adc, uint32_t ul_enable); - -/** - * \brief Indicates write protect status. - * - * \param p_adc Pointer to an ADC instance. - * - * \return 0 if the peripheral is not protected, or 16-bit Write Protect Violation Status. - */ -extern uint32_t adc_get_writeprotect_status(Adc *p_adc); - - -/** - * \brief Checks ADC configurations. - * - * \param p_adc Pointer to an ADC instance. - * \param dw_mck Main clock of the device (value in Hz). - */ -extern void adc_check(Adc* p_adc, uint32_t ul_mck); -#endif - -#if SAM3S || SAM3N || SAM3XA -/** - * \brief Gets PDC registers base address. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval PDC registers base for PDC driver to access. - */ -extern Pdc *adc_get_pdc_base(Adc *p_adc); -#endif - -#if SAM3U - -#ifdef ADC_12B -/** - * \brief Initializes the given ADC with the specified ADC clock and startup time. - * - * \param p_adc Pointer to an ADC instance. - * \param dw_mck Main clock of the device (value in Hz). - * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). - * \param uc_startup ADC start up time value(value in us). Please refer to the product datasheet for details. - * \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details. - * - * \retval 0 The initialization operation succeeds. - * \retval others The initialization operation fails. - */ -extern uint32_t adc_init(Adc12b *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime); -/** - * \brief Configures conversion resolution. - * - * \param p_adc Pointer to an ADC instance. - * \param resolution ADC resolution. - */ -extern void adc_set_resolution(Adc12b *p_adc, adc_resolution_t resolution); -/** - * \brief Configures conversion trigger and free run mode. - * - * \param p_adc Pointer to an ADC instance. - * \param trigger Conversion trigger. - */ -extern void adc_configure_trigger(Adc12b *p_adc, adc_trigger_t trigger); -/** - * \brief Configures ADC power saving mode. - * - * \param p_adc Pointer to an ADC instance. - * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions - * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions - * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) - * 1 Off Mode - */ -extern void adc_configure_power_save(Adc12b *p_adc, uint8_t uc_sleep, uint8_t uc_offmode); -/** - * \brief Configures ADC timing. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. - */ -extern void adc_configure_timing(Adc12b *p_adc, uint32_t ul_sh); -/** - * \brief Starts analog-to-digital conversion. - * - * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. - * - * \param p_adc Pointer to an ADC instance. - */ -extern void adc_start(Adc12b *p_adc); -/** - * \brief Stop analog-to-digital conversion. - * \param p_adc Pointer to an ADC instance. - */ -extern void adc_stop(Adc12b *p_adc); -/** - * \brief Enables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - */ -extern void adc_enable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Disables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - */ -extern void adc_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Reads the ADC channel status. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval 1 means the specified channel is enabled. - * 0 means the specified channel is disabled. - */ -extern uint32_t adc_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Reads the ADC result data of the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval ADC data of the specified channel. - */ -extern uint32_t adc_get_value(Adc12b *p_adc, adc_channel_num_t adc_ch); -/** - * \brief Reads the last ADC result data. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC data. - */ -extern uint32_t adc_get_latest_value(Adc12b *p_adc); - -/** - * \brief Enables differential input for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - */ -extern void adc_enable_differential_input(Adc12b *p_adc); - -/** - * \brief Disables differential input for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_disable_differential_input(Adc12b *p_adc); - -/** - * \brief Enables analog signal offset for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_enable_input_offset(Adc12b *p_adc); - -/** - * \brief Disables analog signal offset for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_disable_input_offset(Adc12b *p_adc); - -/** - * \brief Configures input gain for the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param gain Gain value for the input. - * - */ -extern void adc_set_input_gain(Adc12b *p_adc, adc_gainvalue_t uc_gain); -/** - * \brief Returns the actual ADC clock. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_mck Main clock of the device (value in Hz). - * - * \retval 0 The actual ADC clock (value in Hz). - */ -extern uint32_t adc_get_actual_adc_clock(Adc12b *p_adc, uint32_t ul_mck); - -/** - * \brief Enables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be enabled. - * - */ -extern void adc_enable_interrupt(Adc12b *p_adc, uint32_t ul_source); - -/** - * \brief Disables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be disabled. - */ -extern void adc_disable_interrupt(Adc12b *p_adc, uint32_t ul_source); - -/** \brief Read ADC interrupt mask. - * - * \param p_uart pointer to a UART instance. - * - * \return The interrupt mask value. - */ -extern uint32_t adc_get_interrupt_mask(Adc12b *p_adc); -/** - * \brief Reads ADC interrupt status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC interrupt status. - */ -extern uint32_t adc_get_interrupt_status(Adc12b *p_adc); -/** - * \brief Reads overrun status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC overrun status. - */ -extern uint32_t adc_check_ovr(Adc12b *p_adc,adc_channel_num_t adc_ch); -/** - * \brief Adapts performance versus power consumption. - * - * \note Please refer to ADC Characteristics in the product datasheet for the details. - * - * \param p_adc Pointer to an ADC instance. - * \param ibctl ADC Bias current control. - * - */ -extern void adc_set_bias_current(Adc12b *p_adc, uint8_t uc_ibctl); -/** - * \brief Gets PDC registers base address. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval PDC registers base for PDC driver to access. - */ -extern Pdc *adc_get_pdc_base(Adc12b *p_adc); -#else -/** - * \brief Initializes the given ADC with the specified ADC clock and startup time. - * - * \param p_adc Pointer to an ADC instance. - * \param dw_mck Main clock of the device (value in Hz). - * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). - * \param uc_startup ADC start up time value(value in us). Please refer to the product datasheet for details. - * \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details. - * - * \retval 0 The initialization operation succeeds. - * \retval others The initialization operation fails. - */ -extern uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime); - -/** - * \brief Configures conversion resolution. - * - * \param p_adc Pointer to an ADC instance. - * \param resolution ADC resolution. - * - */ -extern void adc_set_resolution(Adc *p_adc, adc_resolution_t resolution); -/** - * \brief Configures conversion trigger and free run mode. - * - * \param p_adc Pointer to an ADC instance. - * \param trigger Conversion trigger. - * - */ -extern void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger); -/** - * \brief Configures ADC power saving mode. - * - * \param p_adc Pointer to an ADC instance. - * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions - * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions - * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) - * 1 Off Mode - * - */ -extern void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_offmode); -/** - * \brief Configures ADC timing. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. - * - */ -extern void adc_configure_timing(Adc *p_adc, uint32_t ul_sh); -/** - * \brief enable analog change. - * - * note it allows different analog settings for each channel, - * - * \param pAdc Pointer to an Adc instance. - */ -extern void adc_enable_anch( Adc *pAdc ); - -/** - * \brief disable analog change. - * - * note DIFF0, GAIN0 and OFF0 are used for all channels. - * - * \param pAdc Pointer to an Adc instance. - */ -extern void adc_disable_anch( Adc *pAdc ); - -/** - * \brief Starts analog-to-digital conversion. - * - * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. - * - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_start(Adc *p_adc); -/** - * \brief Stop analog-to-digital conversion. - * \param p_adc Pointer to an ADC instance. - * - */ -extern void adc_stop(Adc *p_adc); -/** - * \brief Enables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - */ -extern void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Disables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - */ -extern void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Reads the ADC channel status. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval 1 means the specified channel is enabled. - * 0 means the specified channel is disabled. - */ -extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Reads the ADC result data of the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval ADC data of the specified channel. - */ -extern uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch); - -/** - * \brief Reads the last ADC result data. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC data. - */ -extern uint32_t adc_get_latest_value(Adc *p_adc); - -/** - * \brief Returns the actual ADC clock. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_mck Main clock of the device (value in Hz). - * - * \retval 0 The actual ADC clock (value in Hz). - */ -extern uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck); - -/** - * \brief Enables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be enabled. - * - */ -extern void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source); - -/** - * \brief Disables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be disabled. - * - */ -extern void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source); -/** \brief Read ADC interrupt mask. - * - * \param p_uart pointer to a UART instance. - * - * \return The interrupt mask value. - */ -extern uint32_t adc_get_interrupt_mask(Adc *p_adc); -/** - * \brief Reads ADC interrupt status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC interrupt status. - */ -extern uint32_t adc_get_interrupt_status(Adc *p_adc); - -/** - * \brief Reads overrun status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC overrun status. - */ -extern uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch); - -/** - * \brief Gets PDC registers base address. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval PDC registers base for PDC driver to access. - */ -extern Pdc *adc_get_pdc_base(Adc *p_adc); -#endif - -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - #endif /* #ifndef ADC_H_INCLUDED */ diff --git a/hardware/sam/system/libsam/include/adc10_sam3u.h b/hardware/sam/system/libsam/include/adc10_sam3u.h new file mode 100644 index 000000000..b6257712c --- /dev/null +++ b/hardware/sam/system/libsam/include/adc10_sam3u.h @@ -0,0 +1,276 @@ +/*! \file ********************************************************************* + * + * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller. + * + * ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * - Compiler: IAR EWARM and CodeSourcery GCC for ARM + * - Supported devices: All SAM devices with a Analog-to-Digital Converter can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.com/ + * + *******************************************************************************/ + +#ifndef ADC10_SAM3U_H_INCLUDED +#define ADC10_SAM3U_H_INCLUDED + +#include "../chip.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + + +#if SAM3U + +/** + * \brief Initializes the given ADC with the specified ADC clock and startup time. + * + * \param p_adc Pointer to an ADC instance. + * \param dw_mck Main clock of the device (value in Hz). + * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). + * \param uc_startup ADC start up time value(value in us). Please refer to the product datasheet for details. + * \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details. + * + * \retval 0 The initialization operation succeeds. + * \retval others The initialization operation fails. + */ +extern uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime); + +/** + * \brief Configures conversion resolution. + * + * \param p_adc Pointer to an ADC instance. + * \param resolution ADC resolution. + * + */ +extern void adc_set_resolution(Adc *p_adc, adc_resolution_t resolution); + +/** + * \brief Configures conversion trigger and free run mode. + * + * \param p_adc Pointer to an ADC instance. + * \param trigger Conversion trigger. + * + */ +extern void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger); + +/** + * \brief Configures ADC power saving mode. + * + * \param p_adc Pointer to an ADC instance. + * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions + * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions + * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) + * 1 Off Mode + * + */ +extern void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_offmode); + +/** + * \brief Configures conversion sequence. + * + * \param p_adc Pointer to an ADC instance. + * \param ch_list Channel sequence list. + * \param number Number of channels in the list. + * + */ +extern void adc_configure_sequence(Adc *p_adc, adc_channel_num_t ch_list[], uint8_t uc_num); + +/** + * \brief Configures ADC timing. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. + * + */ +extern void adc_configure_timing(Adc *p_adc, uint32_t ul_sh); + +/** + * \brief Enables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be enabled. + * + */ +extern void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source); + +/** + * \brief Disables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be disabled. + * + */ +extern void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source); + +/** + * \brief Reads ADC interrupt status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC interrupt status. + */ +extern uint32_t adc_get_interrupt_status(Adc *p_adc); + +/** \brief Read ADC interrupt mask. + * + * \param p_uart pointer to a UART instance. + * + * \return The interrupt mask value. + */ +extern uint32_t adc_get_interrupt_mask(Adc *p_adc); + +/** + * \brief Reads overrun status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC overrun status. + */ +extern uint32_t adc_check_ovr(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief enable analog change. + * + * note it allows different analog settings for each channel, + * + * \param pAdc Pointer to an Adc instance. + */ +extern void adc_enable_anch( Adc *pAdc ); + +/** + * \brief disable analog change. + * + * note DIFF0, GAIN0 and OFF0 are used for all channels. + * + * \param pAdc Pointer to an Adc instance. + */ +extern void adc_disable_anch( Adc *pAdc ); + +/** + * \brief Starts analog-to-digital conversion. + * + * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_start( Adc *p_adc ) ; + +/** + * \brief Stop analog-to-digital conversion. + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_stop( Adc *p_adc ) ; + +/** + * \brief Enables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + */ +extern void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Disables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + */ +extern void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the ADC channel status. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval 1 means the specified channel is enabled. + * 0 means the specified channel is disabled. + */ +extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the ADC result data of the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval ADC data of the specified channel. + */ +extern uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the last ADC result data. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC data. + */ +extern uint32_t adc_get_latest_value(Adc *p_adc); + +/** + * \brief Returns the actual ADC clock. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_mck Main clock of the device (value in Hz). + * + * \retval 0 The actual ADC clock (value in Hz). + */ +extern uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck); + +#endif /* SAM3U */ + +/** + * \brief Gets PDC registers base address. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval PDC registers base for PDC driver to access. + */ +extern Pdc *adc_get_pdc_base(Adc *p_adc); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +/**INDENT-ON**/ +/// @endcond + +#endif /* #ifndef ADC10_SAM3U_H_INCLUDED */ diff --git a/hardware/sam/system/libsam/include/adc12_sam3u.h b/hardware/sam/system/libsam/include/adc12_sam3u.h new file mode 100644 index 000000000..3a1699376 --- /dev/null +++ b/hardware/sam/system/libsam/include/adc12_sam3u.h @@ -0,0 +1,257 @@ +/*! \file ********************************************************************* + * + * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller. + * + * ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * - Compiler: IAR EWARM and CodeSourcery GCC for ARM + * - Supported devices: All SAM devices with a Analog-to-Digital Converter can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.com/ + * + *******************************************************************************/ + + + +#ifndef ADC12_H_INCLUDED +#define ADC12_H_INCLUDED + +#include "../chip.h" +/** + * \brief Initializes the given ADC with the specified ADC clock and startup time. + * + * \param p_adc Pointer to an ADC instance. + * \param dw_mck Main clock of the device (value in Hz). + * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). + * \param uc_startup ADC start up time value(value in us). Please refer to the product datasheet for details. + * \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details. + * + * \retval 0 The initialization operation succeeds. + * \retval others The initialization operation fails. + */ +extern uint32_t adc12_init(Adc12b *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime); +/** + * \brief Configures conversion resolution. + * + * \param p_adc Pointer to an ADC instance. + * \param resolution ADC resolution. + */ +extern void adc12_set_resolution(Adc12b *p_adc, adc_resolution_t resolution); +/** + * \brief Configures conversion trigger and free run mode. + * + * \param p_adc Pointer to an ADC instance. + * \param trigger Conversion trigger. + */ +extern void adc12_configure_trigger(Adc12b *p_adc, adc_trigger_t trigger); +/** + * \brief Configures ADC power saving mode. + * + * \param p_adc Pointer to an ADC instance. + * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions + * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions + * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) + * 1 Off Mode + */ +extern void adc12_configure_power_save(Adc12b *p_adc, uint8_t uc_sleep, uint8_t uc_offmode); +/** + * \brief Configures ADC timing. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. + */ +extern void adc12_configure_timing(Adc12b *p_adc, uint32_t ul_sh); +/** + * \brief Starts analog-to-digital conversion. + * + * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. + * + * \param p_adc Pointer to an ADC instance. + */ +extern void adc12_start(Adc12b *p_adc); +/** + * \brief Stop analog-to-digital conversion. + * \param p_adc Pointer to an ADC instance. + */ +extern void adc12_stop(Adc12b *p_adc); +/** + * \brief Enables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + */ +extern void adc12_enable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Disables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + */ +extern void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the ADC channel status. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval 1 means the specified channel is enabled. + * 0 means the specified channel is disabled. + */ +extern uint32_t adc12_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the ADC result data of the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval ADC data of the specified channel. + */ +extern uint32_t adc12_get_value(Adc12b *p_adc, adc_channel_num_t adc_ch); +/** + * \brief Reads the last ADC result data. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC data. + */ +extern uint32_t adc12_get_latest_value(Adc12b *p_adc); + +/** + * \brief Enables differential input for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + */ +extern void adc12_enable_differential_input(Adc12b *p_adc); + +/** + * \brief Disables differential input for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc12_disable_differential_input(Adc12b *p_adc); + +/** + * \brief Enables analog signal offset for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc12_enable_input_offset(Adc12b *p_adc); + +/** + * \brief Disables analog signal offset for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc12_disable_input_offset(Adc12b *p_adc); + +/** + * \brief Configures input gain for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param gain Gain value for the input. + * + */ +extern void adc12_set_input_gain(Adc12b *p_adc, adc_gainvalue_t uc_gain); +/** + * \brief Returns the actual ADC clock. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_mck Main clock of the device (value in Hz). + * + * \retval 0 The actual ADC clock (value in Hz). + */ +extern uint32_t adc12_get_actual_adc_clock(Adc12b *p_adc, uint32_t ul_mck); + +/** + * \brief Enables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be enabled. + * + */ +extern void adc12_enable_interrupt(Adc12b *p_adc, uint32_t ul_source); + +/** + * \brief Disables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be disabled. + */ +extern void adc12_disable_interrupt(Adc12b *p_adc, uint32_t ul_source); + +/** \brief Read ADC interrupt mask. + * + * \param p_uart pointer to a UART instance. + * + * \return The interrupt mask value. + */ +extern uint32_t adc12_get_interrupt_mask(Adc12b *p_adc); +/** + * \brief Reads ADC interrupt status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC interrupt status. + */ +extern uint32_t adc12_get_interrupt_status(Adc12b *p_adc); +/** + * \brief Reads overrun status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC overrun status. + */ +extern uint32_t adc12_check_ovr(Adc12b *p_adc,adc_channel_num_t adc_ch); +/** + * \brief Adapts performance versus power consumption. + * + * \note Please refer to ADC Characteristics in the product datasheet for the details. + * + * \param p_adc Pointer to an ADC instance. + * \param ibctl ADC Bias current control. + * + */ +extern void adc12_set_bias_current(Adc12b *p_adc, uint8_t uc_ibctl); +/** + * \brief Gets PDC registers base address. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval PDC registers base for PDC driver to access. + */ +extern Pdc *adc12_get_pdc_base(Adc12b *p_adc); + +#endif // ADC12_H_INCLUDED diff --git a/hardware/sam/system/libsam/include/adc_sam3snxa.h b/hardware/sam/system/libsam/include/adc_sam3snxa.h new file mode 100644 index 000000000..8ea0d9fee --- /dev/null +++ b/hardware/sam/system/libsam/include/adc_sam3snxa.h @@ -0,0 +1,487 @@ +/*! \file ********************************************************************* + * + * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller. + * + * ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * - Compiler: IAR EWARM and CodeSourcery GCC for ARM + * - Supported devices: All SAM devices with a Analog-to-Digital Converter can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.com/ + * + *******************************************************************************/ + +#ifndef ADC_SAM3SNXA_H_INCLUDED +#define ADC_SAM3SNXA_H_INCLUDED + +#include "../chip.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#if SAM3S || SAM3N || SAM3XA + +/** + * \brief Initializes the given ADC with the specified ADC clock and startup time. + * + * \param p_adc Pointer to an ADC instance. + * \param dw_mck Main clock of the device (value in Hz). + * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). + * \param uc_startup ADC start up time. Please refer to the product datasheet for details. + * + * \retval 0 The initialization operation succeeds. + * \retval others The initialization operation fails. + */ +uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint8_t uc_startup) ; + +/** + * \brief Configures conversion resolution. + * + * \param p_adc Pointer to an ADC instance. + * \param resolution ADC resolution. + * + */ +extern void adc_set_resolution(Adc *p_adc, adc_resolution_t resolution); + +/** + * \brief Configures conversion trigger and free run mode. + * + * \param p_adc Pointer to an ADC instance. + * \param trigger Conversion trigger. + * \param uc_freerun ADC_MR_FREERUN_ON enables freerun mode + * ADC_MR_FREERUN_OFF disables freerun mode + * + */ +extern void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger, uint8_t uc_freerun); + +/** + * \brief Configures ADC power saving mode. + * + * \param p_adc Pointer to an ADC instance. + * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions + * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions + * \param uc_fwup ADC_MR_FWUP_OFF configures sleep mode as uc_sleep setting + * ADC_MR_FWUP_ON keeps voltage reference ON and ADC Core OFF between conversions + * + */ +extern void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_fwup); + +/** + * \brief Configures conversion sequence. + * + * \param p_adc Pointer to an ADC instance. + * \param ch_list Channel sequence list. + * \param number Number of channels in the list. + * + */ +extern void adc_configure_sequence(Adc *p_adc, adc_channel_num_t ch_list[], uint8_t uc_num); + +#if SAM3S || SAM3XA +/** + * \brief Configures ADC timing. + * + * \param p_adc Pointer to an ADC instance. + * \param uc_tracking ADC tracking time = uc_tracking / ADC clock. + * \param uc_settling Analog settling time = (uc_settling + 1) / ADC clock. + * \param uc_transfer Data transfer time = (uc_transfer * 2 + 3) / ADC clock. + * + */ +extern void adc_configure_timing(Adc *p_adc, uint8_t uc_tracking, adc_settling_time_t settling, uint8_t uc_transfer); +#elif SAM3N +/** + * \brief Configures ADC timing. + * + * \param p_adc Pointer to an ADC instance. + * \param uc_tracking ADC tracking time = uc_tracking / ADC clock. + * + */ +extern void adc_configure_timing(Adc *p_adc, uint8_t uc_tracking); +#endif + +#if SAM3S || SAM3XA +/** + * \brief enable analog change. + * + * note it allows different analog settings for each channel, + * + * \param pAdc Pointer to an Adc instance. + */ +extern void adc_enable_anch( Adc *pAdc ); + +/** + * \brief disable analog change. + * + * note DIFF0, GAIN0 and OFF0 are used for all channels. + * + * \param pAdc Pointer to an Adc instance. + */ +extern void adc_disable_anch( Adc *pAdc ); +#endif + +/** + * \brief Starts analog-to-digital conversion. + * + * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_start( Adc *p_adc ) ; + +/** + * \brief Stop analog-to-digital conversion. + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_stop( Adc *p_adc ) ; + +/** + * \brief Enables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + */ +extern void adc_enable_channel( Adc *p_adc, adc_channel_num_t adc_ch ) ; + +/** + * \brief Disables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + */ +extern void adc_disable_channel( Adc *p_adc, adc_channel_num_t adc_ch ) ; + +/** + * \brief Reads the ADC channel status. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval 1 means the specified channel is enabled. + * 0 means the specified channel is disabled. + */ +extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the ADC result data of the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval ADC data of the specified channel. + */ +extern uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch); + +/** + * \brief Reads the last ADC result data. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC data. + */ +extern uint32_t adc_get_latest_value(Adc *p_adc); + +/** + * \brief Enables TAG option so that the number of the last converted channel can be indicated. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_enable_tag(Adc *p_adc); + +/** + * \brief Disables TAG option. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_disable_tag(Adc *p_adc); + +/** + * \brief Indicates the last converted channel. + * + * \note If TAG option is NOT enabled before, an incorrect channel number is returned. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval The last converted channel number. + */ +extern adc_channel_num_t adc_get_tag(Adc *p_adc); + +/** + * \brief Enables conversion sequencer. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_start_sequencer(Adc *p_adc); + +/** + * \brief Disables conversion sequencer. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_stop_sequencer(Adc *p_adc); + +/** + * \brief Configures comparsion mode. + * + * \param p_adc Pointer to an ADC instance. + * \param mode ADC comparsion mode. + * + */ +extern void adc_set_comparison_mode(Adc *p_adc, uint8_t uc_mode); + +/** + * \brief get comparsion mode. + * + * \param p_adc Pointer to an ADC instance. + * \param mode ADC comparsion mode. + * + * \retval compare mode value. + */ +extern uint32_t adc_get_comparison_mode(Adc *p_adc); + +/** + * \brief Configures ADC compare window. + * + * \param p_adc Pointer to an ADC instance. + * \param w_low_threshold Low threshold of compare window. + * \param w_high_threshold High threshold of compare window. + * + */ +extern void adc_set_comparsion_window(Adc *p_adc, uint16_t us_low_threshold, uint16_t us_high_threshold); + +/** + * \brief Configures comparison selected channel. + * + * \param p_adc Pointer to an ADC instance. + * \param channel Comparison selected channel. + * + */ +extern void adc_set_comparison_channel(Adc *p_adc, adc_channel_num_t channel); + +#if SAM3S || SAM3XA +/** + * \brief Enables differential input for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param channel Channel number. + * + */ +extern void adc_enable_differential_input(Adc *p_adc, adc_channel_num_t channel); + +/** + * \brief Disables differential input for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param channel Channel number. + * + */ +extern void adc_disable_differential_input(Adc *p_adc, adc_channel_num_t channel); + +/** + * \brief Enables analog signal offset for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param channel Channel number. + * + */ +extern void adc_enable_input_offset(Adc *p_adc, adc_channel_num_t channel); + +/** + * \brief Disables analog signal offset for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param channel Channel number. + * + */ +extern void adc_disable_input_offset(Adc *p_adc, adc_channel_num_t channel); + +/** + * \brief Configures input gain for the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param channel Channel number. + * \param gain Gain value for the input. + * + */ +extern void adc_set_input_gain(Adc *p_adc, adc_channel_num_t channel, adc_gainvalue_t uc_gain); +#endif + +#if SAM3S8 || SAM3SD8 +/** + * \brief set adc auto calibration mode. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_set_calibmode(Adc *p_adc); +#endif + +/** + * \brief Returns the actual ADC clock. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_mck Main clock of the device (value in Hz). + * + * \retval 0 The actual ADC clock (value in Hz). + */ +extern uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck); + +/** + * \brief Enables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be enabled. + * + */ +extern void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source); + +/** + * \brief Disables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be disabled. + * + */ +extern void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source); + +/** + * \brief Reads ADC interrupt status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC interrupt status. + */ +extern uint32_t adc_get_interrupt_status(Adc *p_adc); + +/** \brief Read ADC interrupt mask. + * + * \param p_uart pointer to a UART instance. + * + * \return The interrupt mask value. + */ +extern uint32_t adc_get_interrupt_mask(Adc *p_adc); + +/** + * \brief Reads overrun status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC overrun status. + */ +extern uint32_t adc_check_ovr(Adc *p_adc, adc_channel_num_t adc_ch); + +#if SAM3S || SAM3XA +/** + * \brief Adapts performance versus power consumption. + * + * \note Please refer to ADC Characteristics in the product datasheet for the details. + * + * \param p_adc Pointer to an ADC instance. + * \param ibctl ADC Bias current control. + * + */ +extern void adc_set_bias_current(Adc *p_adc, uint8_t uc_ibctl); +#endif + +#if SAM3S || SAM3XA +/** + * \brief turn on temperature sensor. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_enable_ts(Adc *p_adc); + +/** + * \brief turn off temperature sensor. + * + * \param p_adc Pointer to an ADC instance. + * + */ +extern void adc_disable_ts(Adc *p_adc); +#endif + +/** + * \brief Enables or disables write protection of ADC registers. + * + * \param p_adc Pointer to an ADC instance. + * \param dw_eanble 1 to eanble, 0 to disable. + */ +extern void adc_set_writeprotect(Adc *p_adc, uint32_t ul_enable); + +/** + * \brief Indicates write protect status. + * + * \param p_adc Pointer to an ADC instance. + * + * \return 0 if the peripheral is not protected, or 16-bit Write Protect Violation Status. + */ +extern uint32_t adc_get_writeprotect_status(Adc *p_adc); + + +/** + * \brief Checks ADC configurations. + * + * \param p_adc Pointer to an ADC instance. + * \param dw_mck Main clock of the device (value in Hz). + */ +extern void adc_check(Adc* p_adc, uint32_t ul_mck); + +/** + * \brief Gets PDC registers base address. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval PDC registers base for PDC driver to access. + */ +extern Pdc *adc_get_pdc_base(Adc *p_adc); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +/**INDENT-ON**/ +/// @endcond + +#endif /* SAM3S || SAM3N || SAM3XA */ + +#endif /* #ifndef ADC_SAM3SNXA_H_INCLUDED */ diff --git a/hardware/sam/system/libsam/source/adc10_sam3u.c b/hardware/sam/system/libsam/source/adc10_sam3u.c new file mode 100644 index 000000000..4fda9ad55 --- /dev/null +++ b/hardware/sam/system/libsam/source/adc10_sam3u.c @@ -0,0 +1,315 @@ +/*! \file ********************************************************************* + * + * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller. + * + * ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * - Compiler: IAR EWARM and CodeSourcery GCC for ARM + * - Supported devices: All SAM devices with a Analog-to-Digital Converter can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.com/ + * + *******************************************************************************/ + +#include "../chip.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +/**INDENT-ON**/ +/// @endcond + +#if SAM3U + +/** + * \brief Initializes the given ADC with the specified ADC clock and startup time. + * + * \param p_adc Pointer to an ADC instance. + * \param dw_mck Main clock of the device (value in Hz). + * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). + * \param ul_startuptime ADC start up time value(value in us). Please refer to the product datasheet for details. + * \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details. + * + * \retval 0 The initialization operation succeeds. + * \retval others The initialization operation fails. + */ +uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime) +{ + uint32_t ul_prescal,ul_startup; + p_adc->ADC_CR = ADC_CR_SWRST; + + /* Reset Mode Register */ + p_adc->ADC_MR = 0; + + /* Reset PDC transfer */ + p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS); + p_adc->ADC_RCR = 0; + p_adc->ADC_RNCR = 0; + p_adc->ADC_TCR = 0; + p_adc->ADC_TNCR = 0; + ul_prescal = ul_mck/(2 * ul_adc_clock) - 1; + ul_startup = ((ul_adc_clock/1000000) * ul_startuptime / 8) - 1; + p_adc->ADC_MR |= ADC_MR_PRESCAL( ul_prescal ) | ( (ul_startup<ADC_MR |= (resolution<<4) & ADC_MR_LOWRES; +} + +/** + * \brief Configures conversion trigger and free run mode. + * + * \param p_adc Pointer to an ADC instance. + * \param trigger Conversion trigger. + */ +void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger) +{ + p_adc->ADC_MR |= trigger; +} +/** + * \brief Configures ADC power saving mode. + * + * \param p_adc Pointer to an ADC instance. + * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions + * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions + * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) + * 1 Off Mode + */ +void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_offmode) +{ + p_adc->ADC_MR |= ((uc_sleep<<5) & ADC_MR_SLEEP) ; +} + +/** + * \brief Configures ADC timing. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. + */ +void adc_configure_timing(Adc *p_adc, uint32_t ul_sh) +{ + p_adc->ADC_MR |= ADC_MR_SHTIM( ul_sh ) ; +} + +/** + * \brief Starts analog-to-digital conversion. + * + * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. + * + * \param p_adc Pointer to an ADC instance. + */ +void adc_start(Adc *p_adc) +{ + p_adc->ADC_CR = ADC_CR_START; +} + +/** + * \brief Stop analog-to-digital conversion. + * \param p_adc Pointer to an ADC instance. + */ +void adc_stop(Adc *p_adc) +{ + p_adc->ADC_CR = ADC_CR_SWRST; +} +/** + * \brief Enables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + */ +void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch) +{ + p_adc->ADC_CHER = 1 << adc_ch; +} + +/** + * \brief Disables the specified ADC channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + */ +void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch) +{ + p_adc->ADC_CHDR = 1 << adc_ch; +} + +/** + * \brief Reads the ADC channel status. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval 1 means the specified channel is enabled. + * 0 means the specified channel is disabled. + */ +uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch) +{ + return p_adc->ADC_CHSR & (1 << adc_ch); +} + +/** + * \brief Reads the ADC result data of the specified channel. + * + * \param p_adc Pointer to an ADC instance. + * \param adc_ch ADC channel number. + * + * \retval ADC data of the specified channel. + */ +uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch) +{ + uint32_t dwData = 0; + + if ( 15 >= adc_ch ) + { + dwData=*(p_adc->ADC_CDR+adc_ch) ; + } + + return dwData ; +} + +/** + * \brief Reads the last ADC result data. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC data. + */ +uint32_t adc_get_latest_value(Adc *p_adc) +{ + return p_adc->ADC_LCDR; +} + +/** + * \brief Returns the actual ADC clock. + * + * \param p_adc Pointer to an ADC instance. + * \param ul_mck Main clock of the device (value in Hz). + * + * \retval 0 The actual ADC clock (value in Hz). + */ +uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck) +{ + uint32_t ul_adcfreq; + uint32_t ul_prescal; + + /* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */ + ul_prescal = (( p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos); + ul_adcfreq = ul_mck / ((ul_prescal+1)*2); + return ul_adcfreq; +} + +/** + * \brief Enables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be enabled. + */ +void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source) +{ + p_adc->ADC_IER = ul_source; +} + +/** + * \brief Disables ADC interrupt(s). + * + * \param p_adc Pointer to an ADC instance. + * \param dw_source Interrupt(s) to be disabled. + */ +void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source) +{ + p_adc->ADC_IDR = ul_source; +} + +/** + * \brief Reads ADC interrupt mask. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC interrupt status. + */ + uint32_t adc_get_interrupt_status(Adc *p_adc) +{ + return p_adc->ADC_SR ; +} + +/** \brief Read ADC interrupt mask. + * + * \param p_uart pointer to a UART instance. + * + * \return The interrupt mask value. + */ +uint32_t adc_get_interrupt_mask(Adc *p_adc) +{ + return p_adc->ADC_IMR; +} + +/** + * \brief Reads overrun status. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval ADC overrun status. + */ +uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch) +{ + return p_adc->ADC_SR & (0x01u << (adc_ch+8)); +} + +/** + * \brief Gets PDC registers base address. + * + * \param p_adc Pointer to an ADC instance. + * + * \retval PDC registers base for PDC driver to access. + */ +Pdc *adc_get_pdc_base(Adc *p_adc) +{ + return PDC_ADC; +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +/**INDENT-ON**/ +/// @endcond + +#endif /* SAM3U */ diff --git a/hardware/sam/system/libsam/source/adc_sam3u.c b/hardware/sam/system/libsam/source/adc12_sam3u.c similarity index 51% rename from hardware/sam/system/libsam/source/adc_sam3u.c rename to hardware/sam/system/libsam/source/adc12_sam3u.c index f928c291e..c2730f59e 100644 --- a/hardware/sam/system/libsam/source/adc_sam3u.c +++ b/hardware/sam/system/libsam/source/adc12_sam3u.c @@ -38,18 +38,18 @@ * *******************************************************************************/ -#include "adc.h" +#include "../chip.h" /// @cond 0 /**INDENT-OFF**/ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /**INDENT-ON**/ /// @endcond + #if SAM3U -#ifdef ADC_12B /** * \brief Initializes the given ADC with the specified ADC clock and startup time. * @@ -62,7 +62,7 @@ extern "C" { * \retval 0 The initialization operation succeeds. * \retval others The initialization operation fails. */ -uint32_t adc_init(Adc12b *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime) +uint32_t adc12_init(Adc12b *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime) { uint32_t ul_prescal,ul_startup,ul_offmode; p_adc->ADC12B_CR = ADC12B_CR_SWRST; @@ -89,7 +89,7 @@ uint32_t adc_init(Adc12b *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_ * \param p_adc Pointer to an ADC instance. * \param resolution ADC resolution. */ -void adc_set_resolution(Adc12b *p_adc, adc_resolution_t resolution) +void adc12_set_resolution(Adc12b *p_adc, adc_resolution_t resolution) { p_adc->ADC12B_MR |= (resolution<<4) & ADC12B_MR_LOWRES; } @@ -99,7 +99,7 @@ void adc_set_resolution(Adc12b *p_adc, adc_resolution_t resolution) * \param p_adc Pointer to an ADC instance. * \param trigger Conversion trigger. */ -void adc_configure_trigger(Adc12b *p_adc, adc_trigger_t trigger) +void adc12_configure_trigger(Adc12b *p_adc, adc_trigger_t trigger) { p_adc->ADC12B_MR |= trigger; } @@ -112,7 +112,7 @@ void adc_configure_trigger(Adc12b *p_adc, adc_trigger_t trigger) * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) * 1 Off Mode */ -void adc_configure_power_save(Adc12b *p_adc, uint8_t uc_sleep, uint8_t uc_offmode) +void adc12_configure_power_save(Adc12b *p_adc, uint8_t uc_sleep, uint8_t uc_offmode) { p_adc->ADC12B_MR |= ((uc_sleep<<5) & ADC12B_MR_SLEEP) ; p_adc->ADC12B_EMR |= uc_offmode; @@ -124,9 +124,9 @@ void adc_configure_power_save(Adc12b *p_adc, uint8_t uc_sleep, uint8_t uc_offmod * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. * */ -void adc_configure_timing(Adc12b *p_adc, uint32_t ul_sh) +void adc12_configure_timing(Adc12b *p_adc, uint32_t ul_sh) { - p_adc->ADC12B_MR |= ADC_MR_SHTIM( ul_sh ) ; + p_adc->ADC12B_MR |= ADC12B_MR_SHTIM( ul_sh ) ; } /** * \brief Starts analog-to-digital conversion. @@ -136,7 +136,7 @@ void adc_configure_timing(Adc12b *p_adc, uint32_t ul_sh) * \param p_adc Pointer to an ADC instance. */ -void adc_start(Adc12b *p_adc) +void adc12_start(Adc12b *p_adc) { p_adc->ADC12B_CR = ADC12B_CR_START; } @@ -144,7 +144,7 @@ void adc_start(Adc12b *p_adc) * \brief Stop analog-to-digital conversion. * \param p_adc Pointer to an ADC instance. */ -void adc_stop(Adc12b *p_adc) +void adc12_stop(Adc12b *p_adc) { p_adc->ADC12B_CR = ADC12B_CR_SWRST; } @@ -154,7 +154,7 @@ void adc_stop(Adc12b *p_adc) * \param p_adc Pointer to an ADC instance. * \param adc_ch ADC channel number. */ -void adc_enable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch) +void adc12_enable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch) { p_adc->ADC12B_CHER = 1 << adc_ch; } @@ -165,7 +165,7 @@ void adc_enable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch) * \param p_adc Pointer to an ADC instance. * \param adc_ch ADC channel number. */ -void adc_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch) +void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch) { p_adc->ADC12B_CHDR = 1 << adc_ch; } @@ -179,7 +179,7 @@ void adc_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch) * \retval 1 means the specified channel is enabled. * 0 means the specified channel is disabled. */ -uint32_t adc_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch) +uint32_t adc12_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch) { return p_adc->ADC12B_CHSR & (1 << adc_ch); } @@ -192,7 +192,7 @@ uint32_t adc_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch) * * \retval ADC data of the specified channel. */ -uint32_t adc_get_value(Adc12b *p_adc, adc_channel_num_t adc_ch) +uint32_t adc12_get_value(Adc12b *p_adc, adc_channel_num_t adc_ch) { uint32_t dwData = 0; @@ -211,7 +211,7 @@ uint32_t adc_get_value(Adc12b *p_adc, adc_channel_num_t adc_ch) * * \retval ADC data. */ -uint32_t adc_get_latest_value(Adc12b *p_adc) +uint32_t adc12_get_latest_value(Adc12b *p_adc) { return p_adc->ADC12B_LCDR; } @@ -220,7 +220,7 @@ uint32_t adc_get_latest_value(Adc12b *p_adc) * * \param p_adc Pointer to an ADC instance. */ - void adc_enable_differential_input(Adc12b *p_adc) + void adc12_enable_differential_input(Adc12b *p_adc) { p_adc->ADC12B_ACR |= (0x01u << 16); } @@ -230,7 +230,7 @@ uint32_t adc_get_latest_value(Adc12b *p_adc) * * \param p_adc Pointer to an ADC instance. */ -void adc_disable_differential_input(Adc12b*p_adc) +void adc12_disable_differential_input(Adc12b*p_adc) { p_adc->ADC12B_ACR &= (0x01u << 16); } @@ -240,7 +240,7 @@ void adc_disable_differential_input(Adc12b*p_adc) * * \param p_adc Pointer to an ADC instance. */ -void adc_enable_input_offset(Adc12b *p_adc) +void adc12_enable_input_offset(Adc12b *p_adc) { p_adc->ADC12B_ACR |= (0x01u << 17); } @@ -250,7 +250,7 @@ void adc_enable_input_offset(Adc12b *p_adc) * * \param p_adc Pointer to an ADC instance. */ -void adc_disable_input_offset(Adc12b *p_adc) +void adc12_disable_input_offset(Adc12b *p_adc) { p_adc->ADC12B_ACR &= (0x01u << 17); } @@ -260,11 +260,11 @@ void adc_disable_input_offset(Adc12b *p_adc) * \param p_adc Pointer to an ADC instance. * \param gain Gain value for the input. */ -void adc_set_input_gain(Adc12b *p_adc, adc_gainvalue_t gain) +void adc12_set_input_gain(Adc12b *p_adc, adc_gainvalue_t gain) { p_adc->ADC12B_ACR |= (0x03u & gain); } -uint32_t adc_get_actual_adc_clock(Adc12b *p_adc, uint32_t ul_mck) +uint32_t adc12_get_actual_adc_clock(Adc12b *p_adc, uint32_t ul_mck) { uint32_t ul_adcfreq; uint32_t ul_prescal; @@ -280,7 +280,7 @@ uint32_t adc_get_actual_adc_clock(Adc12b *p_adc, uint32_t ul_mck) * \param p_adc Pointer to an ADC instance. * \param dw_source Interrupt(s) to be enabled. */ -void adc_enable_interrupt(Adc12b *p_adc, uint32_t ul_source) +void adc12_enable_interrupt(Adc12b *p_adc, uint32_t ul_source) { p_adc->ADC12B_IER = ul_source; } @@ -291,7 +291,7 @@ void adc_enable_interrupt(Adc12b *p_adc, uint32_t ul_source) * \param p_adc Pointer to an ADC instance. * \param dw_source Interrupt(s) to be disabled. */ -void adc_disable_interrupt(Adc12b *p_adc, uint32_t ul_source) +void adc12_disable_interrupt(Adc12b *p_adc, uint32_t ul_source) { p_adc->ADC12B_IDR = ul_source; } @@ -301,7 +301,7 @@ void adc_disable_interrupt(Adc12b *p_adc, uint32_t ul_source) * * \return The interrupt mask value. */ -uint32_t adc_get_interrupt_mask(Adc12b *p_adc) +uint32_t adc12_get_interrupt_mask(Adc12b *p_adc) { return p_adc->ADC12B_IMR; } @@ -312,7 +312,7 @@ uint32_t adc_get_interrupt_mask(Adc12b *p_adc) * * \retval ADC interrupt status. */ -uint32_t adc_get_interrupt_status(Adc12b *p_adc) +uint32_t adc12_get_interrupt_status(Adc12b *p_adc) { return p_adc->ADC12B_SR ; } @@ -323,7 +323,7 @@ uint32_t adc_get_interrupt_status(Adc12b *p_adc) * * \retval ADC overrun status. */ -uint32_t adc_check_ovr(Adc12b *p_adc,adc_channel_num_t adc_ch) +uint32_t adc12_check_ovr(Adc12b *p_adc,adc_channel_num_t adc_ch) { return p_adc->ADC12B_SR & (0x01u << (adc_ch+8)); } @@ -335,7 +335,7 @@ uint32_t adc_check_ovr(Adc12b *p_adc,adc_channel_num_t adc_ch) * \param p_adc Pointer to an ADC instance. * \param ibctl ADC Bias current control. */ -void adc_set_bias_current(Adc12b *p_adc, uint8_t uc_ibctl) +void adc12_set_bias_current(Adc12b *p_adc, uint8_t uc_ibctl) { p_adc->ADC12B_ACR |= ADC12B_ACR_IBCTL(uc_ibctl); } @@ -346,263 +346,17 @@ void adc_set_bias_current(Adc12b *p_adc, uint8_t uc_ibctl) * * \retval PDC registers base for PDC driver to access. */ -Pdc *adc_get_pdc_base(Adc12b *p_adc) +Pdc *adc12_get_pdc_base(Adc12b *p_adc) { return PDC_ADC12B; } -#else -/** - * \brief Initializes the given ADC with the specified ADC clock and startup time. - * - * \param p_adc Pointer to an ADC instance. - * \param dw_mck Main clock of the device (value in Hz). - * \param dw_adc_clock Analog-to-Digital conversion clock (value in Hz). - * \param ul_startuptime ADC start up time value(value in us). Please refer to the product datasheet for details. - * \param ul_offmode_startuptime ADC off mode startup Time value(value in us). Please refer to the product datasheet for details. - * - * \retval 0 The initialization operation succeeds. - * \retval others The initialization operation fails. - */ -uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime) -{ - uint32_t ul_prescal,ul_startup,ul_offmode; - p_adc->ADC_CR = ADC_CR_SWRST; - - /* Reset Mode Register */ - p_adc->ADC_MR = 0; - - /* Reset PDC transfer */ - p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS); - p_adc->ADC_RCR = 0; - p_adc->ADC_RNCR = 0; - p_adc->ADC_TCR = 0; - p_adc->ADC_TNCR = 0; - ul_prescal = ul_mck/(2 * ul_adc_clock) - 1; - ul_startup = ((ul_adc_clock/1000000) * ul_startuptime / 8) - 1; - ul_offmode = ((ul_adc_clock/1000000) * ul_offmode_startuptime / 8) - 1; - p_adc->ADC_MR |= ADC_MR_PRESCAL( ul_prescal ) | ( (ul_startup<ADC_MR |= (resolution<<4) & ADC_MR_LOWRES; -} -/** - * \brief Configures conversion trigger and free run mode. - * - * \param p_adc Pointer to an ADC instance. - * \param trigger Conversion trigger. - */ -void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger) -{ - p_adc->ADC_MR |= trigger; -} -/** - * \brief Configures ADC power saving mode. - * - * \param p_adc Pointer to an ADC instance. - * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions - * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions - * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1) - * 1 Off Mode - */ -void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_offmode) -{ - p_adc->ADC_MR |= ((uc_sleep<<5) & ADC_MR_SLEEP) ; -} -/** - * \brief Configures ADC timing. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_sh ADC sample and hold time = uc_sh / ADC clock. - */ -void adc_configure_timing(Adc *p_adc, uint32_t ul_sh) -{ - p_adc->ADC_MR |= ADC_MR_SHTIM( ul_sh ) ; -} -/** - * \brief Starts analog-to-digital conversion. - * - * \note If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion. - * - * \param p_adc Pointer to an ADC instance. - */ -void adc_start(Adc *p_adc) -{ - p_adc->ADC_CR = ADC_CR_START; -} -/** - * \brief Stop analog-to-digital conversion. - * \param p_adc Pointer to an ADC instance. - */ -void adc_stop(Adc *p_adc) -{ - p_adc->ADC_CR = ADC_CR_SWRST; -} -/** - * \brief Enables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - */ -void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch) -{ - p_adc->ADC_CHER = 1 << adc_ch; -} - -/** - * \brief Disables the specified ADC channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - */ -void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch) -{ - p_adc->ADC_CHDR = 1 << adc_ch; -} - -/** - * \brief Reads the ADC channel status. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval 1 means the specified channel is enabled. - * 0 means the specified channel is disabled. - */ -uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch) -{ - return p_adc->ADC_CHSR & (1 << adc_ch); -} - -/** - * \brief Reads the ADC result data of the specified channel. - * - * \param p_adc Pointer to an ADC instance. - * \param adc_ch ADC channel number. - * - * \retval ADC data of the specified channel. - */ -uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch) -{ - uint32_t dwData = 0; - - if ( 15 >= adc_ch ) - { - dwData=*(p_adc->ADC_CDR+adc_ch) ; - } - - return dwData ; -} - -/** - * \brief Reads the last ADC result data. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC data. - */ -uint32_t adc_get_latest_value(Adc *p_adc) -{ - return p_adc->ADC_LCDR; -} -/** - * \brief Returns the actual ADC clock. - * - * \param p_adc Pointer to an ADC instance. - * \param ul_mck Main clock of the device (value in Hz). - * - * \retval 0 The actual ADC clock (value in Hz). - */ -uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck) -{ - uint32_t ul_adcfreq; - uint32_t ul_prescal; - - /* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */ - ul_prescal = (( p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos); - ul_adcfreq = ul_mck / ((ul_prescal+1)*2); - return ul_adcfreq; -} -/** - * \brief Enables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be enabled. - */ -void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source) -{ - p_adc->ADC_IER = ul_source; -} - -/** - * \brief Disables ADC interrupt(s). - * - * \param p_adc Pointer to an ADC instance. - * \param dw_source Interrupt(s) to be disabled. - */ -void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source) -{ - p_adc->ADC_IDR = ul_source; -} -/** - * \brief Reads ADC interrupt mask. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC interrupt status. - */ - uint32_t adc_get_interrupt_status(Adc *p_adc) -{ - return p_adc->ADC_SR ; -} -/** \brief Read ADC interrupt mask. - * - * \param p_uart pointer to a UART instance. - * - * \return The interrupt mask value. - */ -uint32_t adc_get_interrupt_mask(Adc *p_adc) -{ - return p_adc->ADC_IMR; -} -/** - * \brief Reads overrun status. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval ADC overrun status. - */ -uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch) -{ - return p_adc->ADC_SR & (0x01u << (adc_ch+8)); -} -/** - * \brief Gets PDC registers base address. - * - * \param p_adc Pointer to an ADC instance. - * - * \retval PDC registers base for PDC driver to access. - */ -Pdc *adc_get_pdc_base(Adc *p_adc) -{ - return PDC_ADC; -} -#endif - /// @cond 0 /**INDENT-OFF**/ #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ /**INDENT-ON**/ /// @endcond -#endif +#endif /* SAM3U */ diff --git a/hardware/sam/system/libsam/source/adc.c b/hardware/sam/system/libsam/source/adc_sam3snxa.c similarity index 93% rename from hardware/sam/system/libsam/source/adc.c rename to hardware/sam/system/libsam/source/adc_sam3snxa.c index f21f1d7b0..b610c810f 100644 --- a/hardware/sam/system/libsam/source/adc.c +++ b/hardware/sam/system/libsam/source/adc_sam3snxa.c @@ -38,7 +38,7 @@ * *******************************************************************************/ -#include "adc.h" +#include "../chip.h" /// @cond 0 /**INDENT-OFF**/ @@ -49,6 +49,7 @@ extern "C" { /// @endcond #if SAM3S || SAM3N || SAM3XA + /** * \brief Initializes the given ADC with the specified ADC clock and startup time. * @@ -81,7 +82,6 @@ uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint8_t uc p_adc->ADC_MR |= ADC_MR_PRESCAL( ul_prescal ) | ( (uc_startup<ADC_MR |= (resolution<<4) & ADC_MR_LOWRES; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Configures conversion trigger and free run mode. * @@ -111,9 +108,7 @@ void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger, uint8_t uc_freerun { p_adc->ADC_MR |= trigger | ((uc_freerun<<7) & ADC_MR_FREERUN); } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Configures ADC power saving mode. * @@ -128,9 +123,7 @@ void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_fwup) { p_adc->ADC_MR |= ( ((uc_sleep<<5) & ADC_MR_SLEEP) | ((uc_fwup<<6) & ADC_MR_FWUP) ); } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Configures conversion sequence. * @@ -151,7 +144,7 @@ void adc_configure_sequence(Adc *p_adc, adc_channel_num_t ch_list[], uint8_t uc_ } else { - for(uc_counter=0;uc_counter < 8;uc_counter++) + for(uc_counter=0;uc_counter < 8;uc_counter++) { p_adc->ADC_SEQR1 |= ch_list[uc_counter] << (4*uc_counter); } @@ -161,7 +154,6 @@ void adc_configure_sequence(Adc *p_adc, adc_channel_num_t ch_list[], uint8_t uc_ } } } -#endif #if SAM3S || SAM3XA /** @@ -221,7 +213,6 @@ void adc_disable_anch( Adc *pAdc ) } #endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Starts analog-to-digital conversion. * @@ -235,9 +226,7 @@ void adc_start(Adc *p_adc) { p_adc->ADC_CR = ADC_CR_START; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Stop analog-to-digital conversion. * \param p_adc Pointer to an ADC instance. @@ -247,9 +236,7 @@ void adc_stop(Adc *p_adc) { p_adc->ADC_CR = ADC_CR_SWRST; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Enables the specified ADC channel. * @@ -261,9 +248,7 @@ void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch) { p_adc->ADC_CHER = 1 << adc_ch; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Disables the specified ADC channel. * @@ -275,9 +260,7 @@ void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch) { p_adc->ADC_CHDR = 1 << adc_ch; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Reads the ADC channel status. * @@ -291,9 +274,7 @@ uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch) { return p_adc->ADC_CHSR & (1 << adc_ch); } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Reads the ADC result data of the specified channel. * @@ -313,9 +294,7 @@ uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch) return dwData ; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Reads the last ADC result data. * @@ -327,9 +306,7 @@ uint32_t adc_get_latest_value(Adc *p_adc) { return p_adc->ADC_LCDR; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Enables TAG option so that the number of the last converted channel can be indicated. * @@ -340,9 +317,7 @@ void adc_enable_tag(Adc *p_adc) { p_adc->ADC_EMR |= ADC_EMR_TAG; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Disables TAG option. * @@ -353,9 +328,7 @@ void adc_disable_tag(Adc *p_adc) { p_adc->ADC_EMR &= ~ADC_EMR_TAG; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Indicates the last converted channel. * @@ -369,9 +342,7 @@ adc_channel_num_t adc_get_tag(Adc *p_adc) { return (p_adc->ADC_LCDR & ADC_LCDR_CHNB_Msk) >> ADC_LCDR_CHNB_Pos; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Enables conversion sequencer. * @@ -382,9 +353,7 @@ void adc_start_sequencer(Adc *p_adc) { p_adc->ADC_MR |= ADC_MR_USEQ; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Disables conversion sequencer. * @@ -395,9 +364,7 @@ void adc_stop_sequencer(Adc *p_adc) { p_adc->ADC_MR &= ~ADC_MR_USEQ; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Configures comparsion mode. * @@ -410,9 +377,7 @@ void adc_set_comparison_mode(Adc *p_adc, uint8_t uc_mode) p_adc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPMODE_Msk); p_adc->ADC_EMR |= (uc_mode & ADC_EMR_CMPMODE_Msk); } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief get comparsion mode. * @@ -425,9 +390,7 @@ uint32_t adc_get_comparison_mode(Adc *p_adc) { return p_adc->ADC_EMR & ADC_EMR_CMPMODE_Msk; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Configures ADC compare window. * @@ -440,9 +403,7 @@ void adc_set_comparsion_window(Adc *p_adc, uint16_t us_low_threshold, uint16_t u { p_adc->ADC_CWR = ADC_CWR_LOWTHRES(us_low_threshold) | ADC_CWR_HIGHTHRES(us_high_threshold); } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Configures comparison selected channel. * @@ -463,7 +424,6 @@ void adc_set_comparison_channel(Adc *p_adc, adc_channel_num_t channel) p_adc->ADC_EMR |= ADC_EMR_CMPALL; } } -#endif #if SAM3S || SAM3XA /** @@ -477,9 +437,7 @@ void adc_set_comparison_channel(Adc *p_adc, adc_channel_num_t channel) { p_adc->ADC_COR |= 0x01u << (16+ channel); } -#endif -#if SAM3S || SAM3XA /** * \brief Disables differential input for the specified channel. * @@ -494,9 +452,7 @@ void adc_disable_differential_input(Adc *p_adc, adc_channel_num_t channel) p_adc->ADC_COR &= 0xfffeffffu << channel; p_adc->ADC_COR |= ul_temp; } -#endif -#if SAM3S || SAM3XA /** * \brief Enables analog signal offset for the specified channel. * @@ -508,9 +464,7 @@ void adc_enable_input_offset(Adc *p_adc, adc_channel_num_t channel) { p_adc->ADC_COR |= 0x01u << channel; } -#endif -#if SAM3S || SAM3XA /** * \brief Disables analog signal offset for the specified channel. * @@ -525,9 +479,7 @@ void adc_disable_input_offset(Adc *p_adc, adc_channel_num_t channel) p_adc->ADC_COR &= (0xfffffffeu << channel); p_adc->ADC_COR |= ul_temp; } -#endif -#if SAM3S || SAM3XA /** * \brief Configures input gain for the specified channel. * @@ -540,9 +492,9 @@ void adc_set_input_gain(Adc *p_adc, adc_channel_num_t channel, adc_gainvalue_t g { p_adc->ADC_CGR |= (0x03u << (2*channel)) & (gain << (2*channel)); } -#endif +#endif /* SAM3S || SAM3XA */ -#if SAM3S8 || SAM3SD8 +#if SAM3S8 || SAM3SD8 /** * \brief set adc auto calibration mode. * @@ -553,9 +505,8 @@ void adc_set_calibmode(Adc *p_adc) { p_adc->ADC_CR |= ADC_CR_AUTOCAL; } -#endif +#endif /* SAM3S8 || SAM3SD8 */ -#if SAM3S || SAM3N || SAM3XA /** * \brief Returns the actual ADC clock. * @@ -574,9 +525,7 @@ uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t ul_mck) ul_adcfreq = ul_mck / ((ul_prescal+1)*2); return ul_adcfreq; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Enables ADC interrupt(s). * @@ -588,9 +537,7 @@ void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source) { p_adc->ADC_IER = ul_source; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Disables ADC interrupt(s). * @@ -603,9 +550,6 @@ void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source) p_adc->ADC_IDR = ul_source; } -#endif - -#if SAM3S || SAM3N || SAM3XA /** * \brief Reads ADC interrupt status. * @@ -618,9 +562,6 @@ uint32_t adc_get_interrupt_status(Adc *p_adc) return p_adc->ADC_ISR ; } -#endif - -#if SAM3S || SAM3N || SAM3XA /** \brief Read ADC interrupt mask. * * \param p_uart pointer to a UART instance. @@ -631,9 +572,7 @@ uint32_t adc_get_interrupt_mask(Adc *p_adc) { return p_adc->ADC_IMR; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Reads overrun status. * @@ -645,7 +584,6 @@ uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch) { return p_adc->ADC_OVER & (0x01u << adc_ch); } -#endif #if SAM3S || SAM3XA /** @@ -689,7 +627,6 @@ void adc_disable_ts(Adc *p_adc) } #endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Enables or disables write protection of ADC registers. * @@ -700,9 +637,7 @@ void adc_set_writeprotect(Adc *p_adc, uint32_t ul_enable) { p_adc->ADC_WPMR |= ADC_WPMR_WPKEY(ul_enable); } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief Indicates write protect status. * @@ -714,9 +649,7 @@ uint32_t adc_get_writeprotect_status(Adc *p_adc) { return p_adc->ADC_WPSR & ADC_WPSR_WPVS; } -#endif -#if SAM3S || SAM3N || SAM3XA /** * \brief calcul_startup */ @@ -760,6 +693,7 @@ static uint32_t calcul_startup( uint32_t ul_startup ) return ul_startup_value; } +#if 0 /** * \brief Checks ADC configurations. * @@ -789,7 +723,7 @@ void adc_check(Adc* p_adc, uint32_t ul_mck) ul_startup = (( p_adc->ADC_MR & ADC_MR_STARTUP_Msk) >> ADC_MR_STARTUP_Pos); if( !(p_adc->ADC_MR & ADC_MR_SLEEP_SLEEP) ) { - /* 40µs */ + /* 40ms */ if( ADC_STARTUP_NORM * ul_adcfreq / 1000000 > calcul_startup(ul_startup) ) { printf("Startup time too small: %d, programmed: %d\r\n", (int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000), (int)calcul_startup(ul_startup)); @@ -803,7 +737,7 @@ void adc_check(Adc* p_adc, uint32_t ul_mck) } if( !(p_adc->ADC_MR & ADC_MR_FWUP_ON) ) { - /* Sleep 40µs */ + /* Sleep 40ms */ if( ADC_STARTUP_NORM * ul_adcfreq / 1000000 > calcul_startup(ul_startup) ) { printf("Startup time too small: %d, programmed: %d\r\n", (int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000), (int)(calcul_startup(ul_startup))); @@ -813,7 +747,7 @@ void adc_check(Adc* p_adc, uint32_t ul_mck) { if( p_adc->ADC_MR & ADC_MR_FWUP_ON ) { - /* Fast Wake Up Sleep Mode: 12µs */ + /* Fast Wake Up Sleep Mode: 12ms */ if( ADC_STARTUP_FAST * ul_adcfreq / 1000000 > calcul_startup(ul_startup) ) { printf("Startup time too small: %d, programmed: %d\r\n", (int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000), (int)(calcul_startup(ul_startup))); @@ -822,7 +756,7 @@ void adc_check(Adc* p_adc, uint32_t ul_mck) } } } -#endif +#endif /* 0 */ /** * \brief Gets PDC registers base address. @@ -831,19 +765,18 @@ void adc_check(Adc* p_adc, uint32_t ul_mck) * * \retval PDC registers base for PDC driver to access. */ -#if SAM3S || SAM3N || SAM3XA Pdc *adc_get_pdc_base(Adc *p_adc) { return PDC_ADC; } -#endif + /// @cond 0 /**INDENT-OFF**/ #ifdef __cplusplus } -#endif +#endif // SAM3S || SAM3N || SAM3XA /**INDENT-ON**/ /// @endcond -//#endif /* #ifndef _SAM_ADC_ */ +#endif /* SAM3S || SAM3N || SAM3XA */ diff --git a/hardware/sam/system/libsam/source/pmc.c b/hardware/sam/system/libsam/source/pmc.c index 97240a865..a390d9196 100644 --- a/hardware/sam/system/libsam/source/pmc.c +++ b/hardware/sam/system/libsam/source/pmc.c @@ -83,9 +83,9 @@ extern void PMC_EnablePeripheral( uint32_t dwId ) } } #elif (defined _SAM3N_) || (defined _SAM3U_) - if ( (PMC->PMC_PCSR & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) { - PMC->PMC_PCER = 1 << dwId ; + PMC->PMC_PCER0 = 1 << dwId ; } #else #error "The specified chip is not supported." @@ -121,9 +121,9 @@ extern void PMC_DisablePeripheral( uint32_t dwId ) } } #elif (defined _SAM3N_) || (defined _SAM3U_) - if ( (PMC->PMC_PCSR & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) ) + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) ) { - PMC->PMC_PCDR = 1 << dwId ; + PMC->PMC_PCDR0 = 1 << dwId ; } #else #error "The specified chip is not supported." @@ -169,7 +169,7 @@ extern uint32_t PMC_IsPeripheralEnabled( uint32_t dwId ) } } #elif (defined _SAM3N_) || (defined _SAM3U_) - if ( (PMC->PMC_PCSR & ((uint32_t)1 << dwId)) ) + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) ) { return 0 ; } diff --git a/hardware/sam/variants/arduino_due/variant.cpp b/hardware/sam/variants/arduino_due/variant.cpp index df905e388..b46339124 100644 --- a/hardware/sam/variants/arduino_due/variant.cpp +++ b/hardware/sam/variants/arduino_due/variant.cpp @@ -348,6 +348,38 @@ extern void init( void ) // Initialize Serial port UART, common to all SAM3 variants PIO_Configure( g_APinDescription[PINS_UART].pPort, g_APinDescription[PINS_UART].ulPinType, g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinConfiguration ) ; + + // Initialize 10bit Analog Controller + /* Enable peripheral clock.*/ + PMC_EnablePeripheral( ID_ADC ) ; + + /* Initialize ADC. */ + /* startup = 8: 512 periods of ADCClock + * for prescal = 4 + * prescal: ADCClock = MCK / ( (PRESCAL+1) * 2 ) => 64MHz / ((4+1)*2) = 6.4MHz + * ADC clock = 6.4 MHz + */ + adc_init( ADC, SystemCoreClock, 6400000, 10 ) ; + adc_configure_timing( ADC, 1200 ) ; + adc_configure_trigger( ADC, ADC_TRIG_SW ) ; + adc_disable_interrupt( ADC, 0xFFFFFFFF ) ; /* Disable all adc interrupt. */ + adc_disable_channel( ADC, ADC_ALL_CHANNEL ) ; + + // Initialize 12bit Analog Controller + /* Enable peripheral clock.*/ + PMC_EnablePeripheral( ID_ADC12B ) ; + + /* Initialize ADC12. */ + /* startup = 8: 512 periods of ADCClock + * for prescal = 4 + * prescal: ADCClock = MCK / ( (PRESCAL+1) * 2 ) => 64MHz / ((4+1)*2) = 6.4MHz + * ADC clock = 6.4 MHz + */ + adc12_init( ADC12B, SystemCoreClock, 6400000, 10, 1200 ) ; + adc12_configure_timing( ADC12B, 1200 ) ; + adc12_configure_trigger( ADC12B, ADC_TRIG_SW ) ; + adc12_disable_interrupt( ADC12B, 0xFFFFFFFF ) ; /* Disable all adc interrupt. */ + adc12_disable_channel( ADC12B, ADC_ALL_CHANNEL ) ; } #ifdef __cplusplus }