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https://github.com/arduino/Arduino.git
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[sam] fixing analog on Due, normally
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parent
062278262d
commit
7cbb284eb4
@ -22,8 +22,8 @@
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# putting default variant
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ifeq ("$(VARIANT)", "")
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#VARIANT=sam3s_ek
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VARIANT=sam3u_ek
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#VARIANT=arduino_due
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#VARIANT=sam3u_ek
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VARIANT=arduino_due
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endif
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ifeq ("$(VARIANT)", "sam3s_ek")
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@ -33,15 +33,12 @@ void analogReference( eAnalogReference ulMode )
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uint32_t analogRead( uint32_t ulPin )
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{
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uint32_t ulValue ;
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uint32_t ulValue=0 ;
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uint32_t ulChannel ;
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ulChannel=g_APinDescription[ulPin].ulAnalogChannel ;
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#if defined sam3u_ek
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#elif defined sam3s_ek
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#elif defined arduino_due
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#if defined SAM3U4E
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switch ( ulChannel )
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{
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// Handling ADC 10 bits channels
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@ -53,10 +50,23 @@ uint32_t analogRead( uint32_t ulPin )
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case ADC5 :
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case ADC6 :
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case ADC7 :
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// Enable the corresponding channel
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adc_enable_channel( ADC, ulChannel ) ;
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// Start the ADC
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adc_start( ADC ) ;
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adc_get_value( ADC, ulChannel ) ;
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adc_stop( ADC ) ;
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// Wait for end of conversion
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while ( adc_get_status( ADC ) & (1<<ulChannel) ) == 0 ) ;
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// Read the value
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ulValue=adc_get_value( ADC, ulChannel ) ;
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// Enable the corresponding channel
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adc_disable_channel( ADC, ulChannel ) ;
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// Stop the ADC
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// adc_stop( ADC ) ; // never do adc_stop() else we have to reconfigure the ADC each time
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break ;
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// Handling ADC 12 bits channels
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@ -68,20 +78,32 @@ uint32_t analogRead( uint32_t ulPin )
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case ADC13 :
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case ADC14 :
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case ADC15 :
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// Enable the corresponding channel
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adc12_enable_channel( ADC12B, ulChannel-ADC8 ) ;
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// Start the ADC12B
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adc12_start( ADC12B ) ;
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adc12_get_value( ADC12B, ulChannel-ADC8 ) ;
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adc12_stop( ADC12B ) ;
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// Wait for end of conversion
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while ( adc12_get_status( ADC12B ) & (1<<(ulChannel-ADC8)) ) == 0 ) ;
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// Read the value
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ulValue=adc12_get_value( ADC12B, ulChannel-ADC8 ) ;
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// Stop the ADC12B
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// adc12_stop( ADC12B ) ; // never do adc12_stop() else we have to reconfigure the ADC12B each time
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// Enable the corresponding channel
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adc12_disable_channel( ADC12B, ulChannel-ADC8 ) ;
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break ;
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// Compiler could yell because we don't handle DAC pins
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default :
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ulValue=0 ;
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break ;
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}
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#endif
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return ulValue ;
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}
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@ -99,7 +121,7 @@ void analogWrite( uint32_t ulPin, uint32_t ulValue )
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}
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else
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{
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if ( ulValue == 255)
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if ( ulValue == 255 )
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{
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digitalWrite( ulPin, HIGH ) ;
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}
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@ -153,7 +153,8 @@ create_output:
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$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
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# "$(CC)" -v -c $(CFLAGS) -Wa,aln=$(subst .o,.s,$@) $< -o $@
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@"$(CC)" -c $(CFLAGS) $< -o $@
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# @"$(CC)" -c $(CFLAGS) $< -o $@
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"$(CC)" -c $(CFLAGS) $< -o $@
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$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
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@"$(AS)" -c $(ASFLAGS) $< -o $@
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@ -223,7 +223,16 @@ extern void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch);
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch);
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extern uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch);
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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extern uint32_t adc_get_status(Adc *p_adc);
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/**
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* \brief Reads the ADC result data of the specified channel.
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@ -126,7 +126,16 @@ extern void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch);
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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extern uint32_t adc12_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch);
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extern uint32_t adc12_get_channel_status(Adc12b *p_adc, adc_channel_num_t adc_ch);
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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extern uint32_t adc12_get_status(Adc12b *p_adc);
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/**
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* \brief Reads the ADC result data of the specified channel.
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@ -194,7 +194,25 @@ extern void adc_disable_channel( Adc *p_adc, adc_channel_num_t adc_ch ) ;
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch);
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extern uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch);
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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extern uint32_t adc_get_status(Adc *p_adc);
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/**
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* \brief Reads the ADC overrun status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC ovverrun status register content.
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*/
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extern uint32_t adc_get_overrun_status(Adc *p_adc);
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/**
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* \brief Reads the ADC result data of the specified channel.
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@ -179,11 +179,23 @@ void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch)
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uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch)
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{
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return p_adc->ADC_CHSR & (1 << adc_ch);
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}
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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uint32_t adc_get_status(Adc *p_adc)
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{
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return p_adc->ADC_SR;
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}
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/**
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* \brief Reads the ADC result data of the specified channel.
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*
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@ -179,11 +179,23 @@ void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch)
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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uint32_t adc12_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch)
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uint32_t adc12_get_channel_status(Adc12b *p_adc, adc_channel_num_t adc_ch)
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{
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return p_adc->ADC12B_CHSR & (1 << adc_ch);
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}
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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uint32_t adc12_get_status(Adc12b *p_adc)
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{
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return p_adc->ADC12B_SR;
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}
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/**
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* \brief Reads the ADC result data of the specified channel.
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*
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@ -270,11 +270,35 @@ void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
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* \retval 1 means the specified channel is enabled.
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* 0 means the specified channel is disabled.
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*/
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uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch)
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uint32_t adc_get_channnel_status(Adc *p_adc, adc_channel_num_t adc_ch)
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{
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return p_adc->ADC_CHSR & (1 << adc_ch);
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}
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/**
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* \brief Reads the ADC status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC status register content.
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*/
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uint32_t adc_get_status(Adc *p_adc)
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{
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return p_adc->ADC_ISR;
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}
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/**
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* \brief Reads the ADC overrun status.
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*
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* \param p_adc Pointer to an ADC instance.
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*
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* \retval ADC overrun status register content.
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*/
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uint32_t adc_get_overrun_status(Adc *p_adc)
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{
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return p_adc->ADC_OVER;
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}
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/**
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* \brief Reads the ADC result data of the specified channel.
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*
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@ -40,12 +40,15 @@ MEMORY
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{
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flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
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flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
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sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */
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sram0 (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
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sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
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rom (rx) : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
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ram (rwx) : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 64K */
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ram (rwx) : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
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}
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/* The stack size used by the application. NOTE: you need to adjust */
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STACK_SIZE = 0x2000;
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/* Section Definitions */
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SECTIONS
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{
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@ -136,7 +139,10 @@ SECTIONS
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.stack (NOLOAD):
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{
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. = ALIGN(8);
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*(.stack .stack.*)
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_sstack = .;
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. = . + STACK_SIZE;
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. = ALIGN(8);
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_estack = .;
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} > sram1
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. = ALIGN(4);
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@ -40,12 +40,15 @@ MEMORY
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{
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flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
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flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
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sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */
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sram0 (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
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sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
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rom (rx) : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
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ram (rwx) : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 64K */
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ram (rwx) : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
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}
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/* The stack size used by the application. NOTE: you need to adjust */
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STACK_SIZE = 0x800;
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/* Section Definitions */
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SECTIONS
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{
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@ -128,7 +131,10 @@ SECTIONS
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.stack (NOLOAD):
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{
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. = ALIGN(8);
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*(.stack .stack.*)
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_sstack = .;
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. = . + STACK_SIZE;
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. = ALIGN(8);
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_estack = .;
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} > sram1
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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