[sam] fixing analog on Due, normally

hardware/sam/cores/sam/validation/build_gcc/test.mk

@@ -22,8 +22,8 @@
 # putting default variant
 ifeq ("$(VARIANT)", "")
 #VARIANT=sam3s_ek
-VARIANT=sam3u_ek
+#VARIANT=sam3u_ek
-#VARIANT=arduino_due
+VARIANT=arduino_due
 endif
 
 ifeq ("$(VARIANT)", "sam3s_ek")

hardware/sam/cores/sam/wiring_analog.c

@@ -33,15 +33,12 @@ void analogReference( eAnalogReference ulMode )
 
 uint32_t analogRead( uint32_t ulPin )
 {
-  uint32_t ulValue ;
+  uint32_t ulValue=0 ;
   uint32_t ulChannel ;
 
   ulChannel=g_APinDescription[ulPin].ulAnalogChannel ;
 
-#if defined sam3u_ek
+#if defined SAM3U4E
-#elif defined sam3s_ek
-#elif defined arduino_due
-
   switch ( ulChannel )
   {
     // Handling ADC 10 bits channels
@@ -53,10 +50,23 @@ uint32_t analogRead( uint32_t ulPin )
     case ADC5 :
     case ADC6 :
     case ADC7 :
+      // Enable the corresponding channel
       adc_enable_channel( ADC, ulChannel ) ;
+
+      // Start the ADC
       adc_start( ADC ) ;
-      adc_get_value( ADC, ulChannel ) ;
+
-      adc_stop( ADC ) ;
+      // Wait for end of conversion
+      while ( adc_get_status( ADC ) & (1<<ulChannel) ) == 0 ) ;
+
+      // Read the value
+      ulValue=adc_get_value( ADC, ulChannel ) ;
+
+      // Enable the corresponding channel
+      adc_disable_channel( ADC, ulChannel ) ;
+
+      // Stop the ADC
+//      adc_stop( ADC ) ; // never do adc_stop() else we have to reconfigure the ADC each time
     break ;
 
     // Handling ADC 12 bits channels
@@ -68,20 +78,32 @@ uint32_t analogRead( uint32_t ulPin )
     case ADC13 :
     case ADC14 :
     case ADC15 :
+      // Enable the corresponding channel
       adc12_enable_channel( ADC12B, ulChannel-ADC8 ) ;
+
+      // Start the ADC12B
       adc12_start( ADC12B ) ;
-      adc12_get_value( ADC12B, ulChannel-ADC8 ) ;
+
-      adc12_stop( ADC12B ) ;
+      // Wait for end of conversion
+      while ( adc12_get_status( ADC12B ) & (1<<(ulChannel-ADC8)) ) == 0 ) ;
+
+      // Read the value
+      ulValue=adc12_get_value( ADC12B, ulChannel-ADC8 ) ;
+
+      // Stop the ADC12B
+//      adc12_stop( ADC12B ) ; // never do adc12_stop() else we have to reconfigure the ADC12B each time
+
+      // Enable the corresponding channel
+      adc12_disable_channel( ADC12B, ulChannel-ADC8 ) ;
     break ;
 
     // Compiler could yell because we don't handle DAC pins
     default :
+      ulValue=0 ;
     break ;
   }
 #endif
 
-
-
 	return ulValue ;
 }
 
@@ -99,7 +121,7 @@ void analogWrite( uint32_t ulPin, uint32_t ulValue )
 	}
 	else
   {
-    if ( ulValue == 255)
+    if ( ulValue == 255 )
     {
       digitalWrite( ulPin, HIGH ) ;
     }

hardware/sam/system/libsam/build_gcc/sam3.mk

@@ -153,7 +153,8 @@ create_output:
 
 $(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
 #	"$(CC)" -v -c $(CFLAGS) -Wa,aln=$(subst .o,.s,$@) $< -o $@
-	@"$(CC)" -c $(CFLAGS) $< -o $@
+#	@"$(CC)" -c $(CFLAGS) $< -o $@
+	"$(CC)" -c $(CFLAGS) $< -o $@
 
 $(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
 	@"$(AS)" -c $(ASFLAGS) $< -o $@

hardware/sam/system/libsam/include/adc10_sam3u.h

@@ -223,7 +223,16 @@ extern void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch);
  * \retval 1 means the specified channel is enabled.
  *         0 means the specified channel is disabled.
  */
-extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch);
+extern uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch);
+
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+extern uint32_t adc_get_status(Adc *p_adc);
 
 /**
  * \brief Reads the ADC result data of the specified channel.

hardware/sam/system/libsam/include/adc12_sam3u.h

@@ -126,7 +126,16 @@ extern void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch);
  * \retval 1 means the specified channel is enabled.
  *         0 means the specified channel is disabled.
  */
-extern uint32_t adc12_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch);
+extern uint32_t adc12_get_channel_status(Adc12b *p_adc, adc_channel_num_t adc_ch);
+
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+extern uint32_t adc12_get_status(Adc12b *p_adc);
 
 /**
  * \brief Reads the ADC result data of the specified channel.

hardware/sam/system/libsam/include/adc_sam3snxa.h

@@ -194,7 +194,25 @@ extern void adc_disable_channel( Adc *p_adc, adc_channel_num_t adc_ch ) ;
  * \retval 1 means the specified channel is enabled.
  *         0 means the specified channel is disabled.
  */
-extern uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch);
+extern uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch);
+
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+extern uint32_t adc_get_status(Adc *p_adc);
+
+/**
+ * \brief Reads the ADC overrun status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC ovverrun status register content.
+ */
+extern uint32_t adc_get_overrun_status(Adc *p_adc);
 
 /**
  * \brief Reads the ADC result data of the specified channel.

hardware/sam/system/libsam/source/adc10_sam3u.c

@@ -179,11 +179,23 @@ void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
  * \retval 1 means the specified channel is enabled.
  *         0 means the specified channel is disabled.
  */
-uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch)
+uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch)
 {
     return p_adc->ADC_CHSR & (1 << adc_ch);
 }
 
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+uint32_t adc_get_status(Adc *p_adc)
+{
+    return p_adc->ADC_SR;
+}
+
 /**
  * \brief Reads the ADC result data of the specified channel.
  *

hardware/sam/system/libsam/source/adc12_sam3u.c

@@ -179,11 +179,23 @@ void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch)
  * \retval 1 means the specified channel is enabled.
  *         0 means the specified channel is disabled.
  */
-uint32_t adc12_get_status(Adc12b *p_adc, adc_channel_num_t adc_ch)
+uint32_t adc12_get_channel_status(Adc12b *p_adc, adc_channel_num_t adc_ch)
 {
     return p_adc->ADC12B_CHSR & (1 << adc_ch);
 }
 
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+uint32_t adc12_get_status(Adc12b *p_adc)
+{
+    return p_adc->ADC12B_SR;
+}
+
 /**
  * \brief Reads the ADC result data of the specified channel.
  *

hardware/sam/system/libsam/source/adc_sam3snxa.c

@@ -270,11 +270,35 @@ void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
  * \retval 1 means the specified channel is enabled.
  *         0 means the specified channel is disabled.
  */
-uint32_t adc_get_status(Adc *p_adc, adc_channel_num_t adc_ch)
+uint32_t adc_get_channnel_status(Adc *p_adc, adc_channel_num_t adc_ch)
 {
     return p_adc->ADC_CHSR & (1 << adc_ch);
 }
 
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+uint32_t adc_get_status(Adc *p_adc)
+{
+    return p_adc->ADC_ISR;
+}
+
+/**
+ * \brief Reads the ADC overrun status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC overrun status register content.
+ */
+uint32_t adc_get_overrun_status(Adc *p_adc)
+{
+    return p_adc->ADC_OVER;
+}
+
 /**
  * \brief Reads the ADC result data of the specified channel.
  *

hardware/sam/variants/sam3u_ek/linker_scripts/gcc/flash.ld

@@ -40,12 +40,15 @@ MEMORY
 {
 	flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
 	flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
-	sram0  (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */
+	sram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
 	sram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
 	rom (rx)    : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
-	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 64K */
+	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
 }
 
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = 0x2000;
+
 /* Section Definitions */ 
 SECTIONS 
 { 
@@ -136,7 +139,10 @@ SECTIONS
     .stack (NOLOAD):
     {
         . = ALIGN(8);
-        *(.stack .stack.*)
+         _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
     } > sram1
 
     . = ALIGN(4); 

hardware/sam/variants/sam3u_ek/linker_scripts/gcc/sram.ld

@@ -40,12 +40,15 @@ MEMORY
 {
 	flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
 	flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
-	sram0  (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */
+	sram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
 	sram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
 	rom (rx)    : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
-	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 64K */
+	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
 }
 
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = 0x800;
+
 /* Section Definitions */ 
 SECTIONS 
 { 
@@ -128,7 +131,10 @@ SECTIONS
     .stack (NOLOAD):
     {
         . = ALIGN(8);
-        *(.stack .stack.*)
+         _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
     } > sram1
 
     /* .ARM.exidx is sorted, so has to go in its own output section.  */