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https://github.com/arduino/Arduino.git
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Merge commit 'collin80-uart-fix' into ide-1.5.x
This commit is contained in:
commit
91e6926cfc
@ -6,6 +6,9 @@ The following changes are included also in the Arduino IDE 1.0.7:
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[ide]
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[ide]
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* Mitigated Serial Monitor resource exhaustion when the connected device sends a lot of data (Paul Stoffregen)
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* Mitigated Serial Monitor resource exhaustion when the connected device sends a lot of data (Paul Stoffregen)
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[core]
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* sam: HardwareSerial now performs ISR based buffered transmission (Collin Kidder)
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ARDUINO 1.6.0rc1
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ARDUINO 1.6.0rc1
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* IDE internals have been refactored and sorted out. (Claudio Indellicati)
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* IDE internals have been refactored and sorted out. (Claudio Indellicati)
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@ -21,7 +21,7 @@
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RingBuffer::RingBuffer( void )
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RingBuffer::RingBuffer( void )
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{
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{
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memset( _aucBuffer, 0, SERIAL_BUFFER_SIZE ) ;
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memset( (void *)_aucBuffer, 0, SERIAL_BUFFER_SIZE ) ;
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_iHead=0 ;
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_iHead=0 ;
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_iTail=0 ;
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_iTail=0 ;
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}
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}
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@ -25,14 +25,14 @@
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// using a ring buffer (I think), in which head is the index of the location
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// using a ring buffer (I think), in which head is the index of the location
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// to which to write the next incoming character and tail is the index of the
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// to which to write the next incoming character and tail is the index of the
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// location from which to read.
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// location from which to read.
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#define SERIAL_BUFFER_SIZE 64
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#define SERIAL_BUFFER_SIZE 128
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class RingBuffer
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class RingBuffer
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{
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{
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public:
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public:
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uint8_t _aucBuffer[SERIAL_BUFFER_SIZE] ;
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volatile uint8_t _aucBuffer[SERIAL_BUFFER_SIZE] ;
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int _iHead ;
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volatile int _iHead ;
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int _iTail ;
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volatile int _iTail ;
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public:
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public:
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RingBuffer( void ) ;
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RingBuffer( void ) ;
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@ -23,33 +23,39 @@
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// Constructors ////////////////////////////////////////////////////////////////
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// Constructors ////////////////////////////////////////////////////////////////
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UARTClass::UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer )
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UARTClass::UARTClass( Uart *pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer *pRx_buffer, RingBuffer *pTx_buffer )
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{
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{
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_rx_buffer = pRx_buffer ;
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_rx_buffer = pRx_buffer;
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_tx_buffer = pTx_buffer;
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_pUart=pUart ;
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_pUart=pUart;
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_dwIrq=dwIrq ;
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_dwIrq=dwIrq;
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_dwId=dwId ;
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_dwId=dwId;
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}
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}
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// Public Methods //////////////////////////////////////////////////////////////
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// Public Methods //////////////////////////////////////////////////////////////
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void UARTClass::begin( const uint32_t dwBaudRate )
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void UARTClass::begin( const uint32_t dwBaudRate )
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|
{
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begin( dwBaudRate, UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL );
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|
}
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void UARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
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{
|
{
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// Configure PMC
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// Configure PMC
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pmc_enable_periph_clk( _dwId ) ;
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pmc_enable_periph_clk( _dwId );
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// Disable PDC channel
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// Disable PDC channel
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_pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS ;
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_pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
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// Reset and disable receiver and transmitter
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// Reset and disable receiver and transmitter
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_pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS ;
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_pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
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// Configure mode
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// Configure mode
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_pUart->UART_MR = UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL ;
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_pUart->UART_MR = config;
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// Configure baudrate (asynchronous, no oversampling)
|
// Configure baudrate (asynchronous, no oversampling)
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_pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4 ;
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_pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4;
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// Configure interrupts
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// Configure interrupts
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_pUart->UART_IDR = 0xFFFFFFFF;
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_pUart->UART_IDR = 0xFFFFFFFF;
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@ -58,63 +64,99 @@ void UARTClass::begin( const uint32_t dwBaudRate )
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// Enable UART interrupt in NVIC
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// Enable UART interrupt in NVIC
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NVIC_EnableIRQ(_dwIrq);
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NVIC_EnableIRQ(_dwIrq);
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// Make sure both ring buffers are initialized back to empty.
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_rx_buffer->_iHead = _rx_buffer->_iTail = 0;
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_tx_buffer->_iHead = _tx_buffer->_iTail = 0;
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// Enable receiver and transmitter
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// Enable receiver and transmitter
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_pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN ;
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_pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
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}
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}
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void UARTClass::end( void )
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void UARTClass::end( void )
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{
|
{
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// clear any received data
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// Clear any received data
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_rx_buffer->_iHead = _rx_buffer->_iTail ;
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_rx_buffer->_iHead = _rx_buffer->_iTail;
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( _dwIrq ) ;
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// Wait for any outstanding data to be sent
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// Wait for any outstanding data to be sent
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flush();
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flush();
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pmc_disable_periph_clk( _dwId ) ;
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( _dwIrq );
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pmc_disable_periph_clk( _dwId );
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}
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void UARTClass::setInterruptPriority(uint32_t priority)
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|
{
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NVIC_SetPriority(_dwIrq, priority & 0x0F);
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|
}
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uint32_t UARTClass::getInterruptPriority()
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{
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return NVIC_GetPriority(_dwIrq);
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}
|
}
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int UARTClass::available( void )
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int UARTClass::available( void )
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{
|
{
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return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ;
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return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE;
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|
}
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int UARTClass::availableForWrite(void)
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{
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int head = _tx_buffer->_iHead;
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int tail = _tx_buffer->_iTail;
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if (head >= tail) return SERIAL_BUFFER_SIZE - 1 - head + tail;
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return tail - head - 1;
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}
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}
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int UARTClass::peek( void )
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int UARTClass::peek( void )
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{
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{
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if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
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if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
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return -1 ;
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return -1;
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return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
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return _rx_buffer->_aucBuffer[_rx_buffer->_iTail];
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}
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}
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int UARTClass::read( void )
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int UARTClass::read( void )
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{
|
{
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// if the head isn't ahead of the tail, we don't have any characters
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// if the head isn't ahead of the tail, we don't have any characters
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if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
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if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
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return -1 ;
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return -1;
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uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
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uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail];
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_rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ;
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_rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE;
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return uc ;
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return uc;
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}
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}
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||||||
|
|
||||||
void UARTClass::flush( void )
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void UARTClass::flush( void )
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{
|
{
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||||||
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while (_tx_buffer->_iHead != _tx_buffer->_iTail); //wait for transmit data to be sent
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// Wait for transmission to complete
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// Wait for transmission to complete
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||||||
while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
|
while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
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;
|
;
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}
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}
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|
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size_t UARTClass::write( const uint8_t uc_data )
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size_t UARTClass::write( const uint8_t uc_data )
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||||||
{
|
{
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// Check if the transmitter is ready
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// Is the hardware currently busy?
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while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
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if (((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) |
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;
|
(_tx_buffer->_iTail != _tx_buffer->_iHead))
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|
{
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// If busy we buffer
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unsigned int l = (_tx_buffer->_iHead + 1) % SERIAL_BUFFER_SIZE;
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|
while (_tx_buffer->_iTail == l)
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|
; // Spin locks if we're about to overwrite the buffer. This continues once the data is sent
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// Send character
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_tx_buffer->_aucBuffer[_tx_buffer->_iHead] = uc_data;
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_pUart->UART_THR = uc_data;
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_tx_buffer->_iHead = l;
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// Make sure TX interrupt is enabled
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_pUart->UART_IER = UART_IER_TXRDY;
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|
}
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else
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{
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// Bypass buffering and send character directly
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_pUart->UART_THR = uc_data;
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|
}
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return 1;
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return 1;
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}
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}
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@ -122,15 +164,28 @@ void UARTClass::IrqHandler( void )
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{
|
{
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uint32_t status = _pUart->UART_SR;
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uint32_t status = _pUart->UART_SR;
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|
|
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// Did we receive data ?
|
// Did we receive data?
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if ((status & UART_SR_RXRDY) == UART_SR_RXRDY)
|
if ((status & UART_SR_RXRDY) == UART_SR_RXRDY)
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_rx_buffer->store_char(_pUart->UART_RHR);
|
_rx_buffer->store_char(_pUart->UART_RHR);
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|
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// Acknowledge errors
|
// Do we need to keep sending data?
|
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if ((status & UART_SR_OVRE) == UART_SR_OVRE ||
|
if ((status & UART_SR_TXRDY) == UART_SR_TXRDY)
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(status & UART_SR_FRAME) == UART_SR_FRAME)
|
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{
|
{
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// TODO: error reporting outside ISR
|
if (_tx_buffer->_iTail != _tx_buffer->_iHead) {
|
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|
_pUart->UART_THR = _tx_buffer->_aucBuffer[_tx_buffer->_iTail];
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|
_tx_buffer->_iTail = (unsigned int)(_tx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE;
|
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|
}
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|
else
|
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|
{
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|
// Mask off transmit interrupt so we don't get it anymore
|
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_pUart->UART_IDR = UART_IDR_TXRDY;
|
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|
}
|
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|
}
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|
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|
// Acknowledge errors
|
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|
if ((status & UART_SR_OVRE) == UART_SR_OVRE || (status & UART_SR_FRAME) == UART_SR_FRAME)
|
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|
{
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|
// TODO: error reporting outside ISR
|
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_pUart->UART_CR |= UART_CR_RSTSTA;
|
_pUart->UART_CR |= UART_CR_RSTSTA;
|
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}
|
}
|
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}
|
}
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|
@ -28,32 +28,32 @@
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class UARTClass : public HardwareSerial
|
class UARTClass : public HardwareSerial
|
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{
|
{
|
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protected:
|
protected:
|
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RingBuffer *_rx_buffer ;
|
RingBuffer *_rx_buffer;
|
||||||
|
RingBuffer *_tx_buffer;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
Uart* _pUart ;
|
Uart* _pUart;
|
||||||
IRQn_Type _dwIrq ;
|
IRQn_Type _dwIrq;
|
||||||
uint32_t _dwId ;
|
uint32_t _dwId;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ;
|
UARTClass(Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
|
||||||
|
|
||||||
void begin( const uint32_t dwBaudRate ) ;
|
void begin(const uint32_t dwBaudRate);
|
||||||
void end( void ) ;
|
void begin(const uint32_t dwBaudRate, const uint32_t config);
|
||||||
int available( void ) ;
|
void end(void);
|
||||||
int peek( void ) ;
|
int available(void);
|
||||||
int read( void ) ;
|
int availableForWrite(void);
|
||||||
void flush( void ) ;
|
int peek(void);
|
||||||
size_t write( const uint8_t c ) ;
|
int read(void);
|
||||||
|
void flush(void);
|
||||||
|
size_t write(const uint8_t c);
|
||||||
|
using Print::write; // pull in write(str) and write(buf, size) from Print
|
||||||
|
|
||||||
void IrqHandler( void ) ;
|
void setInterruptPriority(uint32_t priority);
|
||||||
|
uint32_t getInterruptPriority();
|
||||||
|
|
||||||
#if defined __GNUC__ /* GCC CS3 */
|
void IrqHandler(void);
|
||||||
using Print::write ; // pull in write(str) and write(buf, size) from Print
|
|
||||||
#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */
|
|
||||||
// virtual void write( const char *str ) ;
|
|
||||||
// virtual void write( const uint8_t *buffer, size_t size ) ;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
operator bool() { return true; }; // UART always active
|
operator bool() { return true; }; // UART always active
|
||||||
};
|
};
|
||||||
|
@ -23,121 +23,17 @@
|
|||||||
|
|
||||||
// Constructors ////////////////////////////////////////////////////////////////
|
// Constructors ////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer )
|
USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer )
|
||||||
|
: UARTClass((Uart*)pUsart, dwIrq, dwId, pRx_buffer, pTx_buffer)
|
||||||
{
|
{
|
||||||
_rx_buffer = pRx_buffer ;
|
// In case anyone needs USART specific functionality in the future
|
||||||
|
_pUsart=pUsart;
|
||||||
_pUsart=pUsart ;
|
|
||||||
_dwIrq=dwIrq ;
|
|
||||||
_dwId=dwId ;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Public Methods //////////////////////////////////////////////////////////////
|
// Public Methods //////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
void USARTClass::begin( const uint32_t dwBaudRate )
|
|
||||||
{
|
|
||||||
begin( dwBaudRate, SERIAL_8N1 );
|
|
||||||
}
|
|
||||||
|
|
||||||
void USARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
|
void USARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
|
||||||
{
|
{
|
||||||
// Configure PMC
|
UARTClass::begin(dwBaudRate, config);
|
||||||
pmc_enable_periph_clk( _dwId ) ;
|
|
||||||
|
|
||||||
// Disable PDC channel
|
|
||||||
_pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS ;
|
|
||||||
|
|
||||||
// Reset and disable receiver and transmitter
|
|
||||||
_pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS ;
|
|
||||||
|
|
||||||
// Configure mode
|
|
||||||
_pUsart->US_MR = config;
|
|
||||||
|
|
||||||
|
|
||||||
// Configure baudrate, asynchronous no oversampling
|
|
||||||
_pUsart->US_BRGR = (SystemCoreClock / dwBaudRate) / 16 ;
|
|
||||||
|
|
||||||
// Configure interrupts
|
|
||||||
_pUsart->US_IDR = 0xFFFFFFFF;
|
|
||||||
_pUsart->US_IER = US_IER_RXRDY | US_IER_OVRE | US_IER_FRAME;
|
|
||||||
|
|
||||||
// Enable UART interrupt in NVIC
|
|
||||||
NVIC_EnableIRQ( _dwIrq ) ;
|
|
||||||
|
|
||||||
// Enable receiver and transmitter
|
|
||||||
_pUsart->US_CR = US_CR_RXEN | US_CR_TXEN ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void USARTClass::end( void )
|
|
||||||
{
|
|
||||||
// clear any received data
|
|
||||||
_rx_buffer->_iHead = _rx_buffer->_iTail ;
|
|
||||||
|
|
||||||
// Disable UART interrupt in NVIC
|
|
||||||
NVIC_DisableIRQ( _dwIrq ) ;
|
|
||||||
|
|
||||||
// Wait for any outstanding data to be sent
|
|
||||||
flush();
|
|
||||||
|
|
||||||
pmc_disable_periph_clk( _dwId ) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
int USARTClass::available( void )
|
|
||||||
{
|
|
||||||
return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ;
|
|
||||||
}
|
|
||||||
|
|
||||||
int USARTClass::peek( void )
|
|
||||||
{
|
|
||||||
if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
|
|
||||||
return -1 ;
|
|
||||||
|
|
||||||
return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
|
|
||||||
}
|
|
||||||
|
|
||||||
int USARTClass::read( void )
|
|
||||||
{
|
|
||||||
// if the head isn't ahead of the tail, we don't have any characters
|
|
||||||
if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
|
|
||||||
return -1 ;
|
|
||||||
|
|
||||||
uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
|
|
||||||
_rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ;
|
|
||||||
return uc ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void USARTClass::flush( void )
|
|
||||||
{
|
|
||||||
// Wait for transmission to complete
|
|
||||||
while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
|
|
||||||
;
|
|
||||||
}
|
|
||||||
|
|
||||||
size_t USARTClass::write( const uint8_t uc_data )
|
|
||||||
{
|
|
||||||
// Check if the transmitter is ready
|
|
||||||
while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
|
|
||||||
;
|
|
||||||
|
|
||||||
// Send character
|
|
||||||
_pUsart->US_THR = uc_data ;
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
void USARTClass::IrqHandler( void )
|
|
||||||
{
|
|
||||||
uint32_t status = _pUsart->US_CSR;
|
|
||||||
|
|
||||||
// Did we receive data ?
|
|
||||||
if ((status & US_CSR_RXRDY) == US_CSR_RXRDY)
|
|
||||||
_rx_buffer->store_char( _pUsart->US_RHR ) ;
|
|
||||||
|
|
||||||
// Acknowledge errors
|
|
||||||
if ((status & US_CSR_OVRE) == US_CSR_OVRE ||
|
|
||||||
(status & US_CSR_FRAME) == US_CSR_FRAME)
|
|
||||||
{
|
|
||||||
// TODO: error reporting outside ISR
|
|
||||||
_pUsart->US_CR |= US_CR_RSTSTA;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -19,7 +19,7 @@
|
|||||||
#ifndef _USART_CLASS_
|
#ifndef _USART_CLASS_
|
||||||
#define _USART_CLASS_
|
#define _USART_CLASS_
|
||||||
|
|
||||||
#include "HardwareSerial.h"
|
#include "UARTClass.h"
|
||||||
#include "RingBuffer.h"
|
#include "RingBuffer.h"
|
||||||
|
|
||||||
// Includes Atmel CMSIS
|
// Includes Atmel CMSIS
|
||||||
@ -56,38 +56,16 @@
|
|||||||
#define SERIAL_7O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
#define SERIAL_7O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||||
#define SERIAL_8O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
#define SERIAL_8O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||||
|
|
||||||
class USARTClass : public HardwareSerial
|
class USARTClass : public UARTClass
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
RingBuffer *_rx_buffer ;
|
Usart* _pUsart;
|
||||||
|
|
||||||
protected:
|
|
||||||
Usart* _pUsart ;
|
|
||||||
IRQn_Type _dwIrq ;
|
|
||||||
uint32_t _dwId ;
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ;
|
USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer );
|
||||||
|
|
||||||
void begin( const uint32_t dwBaudRate ) ;
|
void begin( const uint32_t dwBaudRate , const uint32_t config );
|
||||||
void begin( const uint32_t dwBaudRate , const uint32_t config ) ;
|
using UARTClass::begin; // Needed only for polymorphic methods
|
||||||
void end( void ) ;
|
|
||||||
int available( void ) ;
|
|
||||||
int peek( void ) ;
|
|
||||||
int read( void ) ;
|
|
||||||
void flush( void ) ;
|
|
||||||
size_t write( const uint8_t c ) ;
|
|
||||||
|
|
||||||
void IrqHandler( void ) ;
|
|
||||||
|
|
||||||
#if defined __GNUC__ /* GCC CS3 */
|
|
||||||
using Print::write ; // pull in write(str) and write(buf, size) from Print
|
|
||||||
#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */
|
|
||||||
// virtual void write( const char *str ) ;
|
|
||||||
// virtual void write( const uint8_t *buffer, size_t size ) ;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
operator bool() { return true; }; // USART always active
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // _USART_CLASS_
|
#endif // _USART_CLASS_
|
||||||
|
@ -299,8 +299,9 @@ extern const PinDescription g_APinDescription[]=
|
|||||||
* UART objects
|
* UART objects
|
||||||
*/
|
*/
|
||||||
RingBuffer rx_buffer1;
|
RingBuffer rx_buffer1;
|
||||||
|
RingBuffer tx_buffer1;
|
||||||
|
|
||||||
UARTClass Serial(UART, UART_IRQn, ID_UART, &rx_buffer1);
|
UARTClass Serial(UART, UART_IRQn, ID_UART, &rx_buffer1, &tx_buffer1);
|
||||||
void serialEvent() __attribute__((weak));
|
void serialEvent() __attribute__((weak));
|
||||||
void serialEvent() { }
|
void serialEvent() { }
|
||||||
|
|
||||||
@ -317,14 +318,17 @@ void UART_Handler(void)
|
|||||||
RingBuffer rx_buffer2;
|
RingBuffer rx_buffer2;
|
||||||
RingBuffer rx_buffer3;
|
RingBuffer rx_buffer3;
|
||||||
RingBuffer rx_buffer4;
|
RingBuffer rx_buffer4;
|
||||||
|
RingBuffer tx_buffer2;
|
||||||
|
RingBuffer tx_buffer3;
|
||||||
|
RingBuffer tx_buffer4;
|
||||||
|
|
||||||
USARTClass Serial1(USART0, USART0_IRQn, ID_USART0, &rx_buffer2);
|
USARTClass Serial1(USART0, USART0_IRQn, ID_USART0, &rx_buffer2, &tx_buffer2);
|
||||||
void serialEvent1() __attribute__((weak));
|
void serialEvent1() __attribute__((weak));
|
||||||
void serialEvent1() { }
|
void serialEvent1() { }
|
||||||
USARTClass Serial2(USART1, USART1_IRQn, ID_USART1, &rx_buffer3);
|
USARTClass Serial2(USART1, USART1_IRQn, ID_USART1, &rx_buffer3, &tx_buffer3);
|
||||||
void serialEvent2() __attribute__((weak));
|
void serialEvent2() __attribute__((weak));
|
||||||
void serialEvent2() { }
|
void serialEvent2() { }
|
||||||
USARTClass Serial3(USART3, USART3_IRQn, ID_USART3, &rx_buffer4);
|
USARTClass Serial3(USART3, USART3_IRQn, ID_USART3, &rx_buffer4, &tx_buffer4);
|
||||||
void serialEvent3() __attribute__((weak));
|
void serialEvent3() __attribute__((weak));
|
||||||
void serialEvent3() { }
|
void serialEvent3() { }
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user