mirror of
https://github.com/arduino/Arduino.git
synced 2025-01-30 19:52:13 +01:00
[sam] fixing libsam and adding support of due_x
This commit is contained in:
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parent
33d4e07315
commit
aa3dde0973
@ -1,6 +1,11 @@
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set Path=%ARM_GCC_TOOLCHAIN%
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export Path
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start "libsam" /d"system\libsam\build_gcc" /max "cd"
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start "libarduino" /d"cores\sam\build_gcc" /max "cd"
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start "libvariant sam3s-ek" /d"variants\sam3s_ek\build_gcc" /max "cd"
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start "libvariant sam3u-ek" /d"variants\sam3u_ek\build_gcc" /max "cd"
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start "libvariant Arduino Due" /d"variants\arduino_due\build_gcc" /max "cd"
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start "libvariant sam3x-ek" /d"variants\sam3x_ek\build_gcc" /max "cd"
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start "libvariant Arduino Due U" /d"variants\arduino_due_u\build_gcc" /max "cd"
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start "libvariant Arduino Due X" /d"variants\arduino_due_x\build_gcc" /max "cd"
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start "test" /d"cores\sam\validation\build_gcc" /max "cd"
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@ -8,7 +8,7 @@
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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# See the GNU Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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@ -24,48 +24,87 @@ SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
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# Rules
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#-------------------------------------------------------------------------------
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# libsam_sam3s4c_gcc_rel.a libsam_sam3u4e_gcc_rel.a
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all: libsam_sam3s4c_gcc_dbg.a libsam_sam3u4e_gcc_dbg.a
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# libsam_sam3s4c_gcc_rel.a libsam_sam3u4e_gcc_rel.a libsam_sam3x8e_gcc_rel.a libsam_sam3x8h_gcc_rel.a
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all: libsam_sam3s4c_gcc_dbg.a libsam_sam3u4e_gcc_dbg.a libsam_sam3x8e_gcc_dbg.a libsam_sam3x8h_gcc_dbg.a
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arduino_due:
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@echo ---
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@echo ---
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arduino_due_u:
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@echo ---
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@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) OUTPUT_BIN=../../../variants/arduino_due -f sam3.mk
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arduino_due_x:
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@$(MAKE) CHIP=__SAM3X8E__ $(SUBMAKE_OPTIONS) OUTPUT_BIN=../../../variants/arduino_due -f sam3.mk
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.PHONY: libsam_sam3s4c_gcc_dbg.a
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libsam_sam3s4c_gcc_dbg.a:
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@echo ---
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@echo ---
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@echo ---
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@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3s4c_gcc_rel.a
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libsam_sam3s4c_gcc_rel.a:
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@echo ---
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@echo ---
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@echo ---
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@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3u4e_gcc_dbg.a
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libsam_sam3u4e_gcc_dbg.a:
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@echo ---
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@echo ---
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@echo ---
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@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3u4e_gcc_rel.a
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libsam_sam3u4e_gcc_rel.a:
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@echo ---
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@echo ---
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@echo ---
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@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3x8e_gcc_dbg.a
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libsam_sam3x8e_gcc_dbg.a:
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@$(MAKE) CHIP=__SAM3X8E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3x8e_gcc_rel.a
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libsam_sam3x8e_gcc_rel.a:
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@$(MAKE) CHIP=__SAM3X8E__ $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3x8h_gcc_dbg.a
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libsam_sam3x8h_gcc_dbg.a:
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@$(MAKE) CHIP=__SAM3X8H__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: libsam_sam3x8h_gcc_rel.a
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libsam_sam3x8h_gcc_rel.a:
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@echo ---
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@echo ---
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@echo --- Making $@
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@echo ---
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@$(MAKE) CHIP=__SAM3X8H__ $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: clean
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clean:
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@echo --- Cleaning sam3s4c release and debug
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@ -76,4 +115,12 @@ clean:
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@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@echo --- Cleaning sam3x8e release and debug
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@$(MAKE) CHIP=__SAM3X8E__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@$(MAKE) CHIP=__SAM3X8E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@echo --- Cleaning sam3x8h release and debug
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@$(MAKE) CHIP=__SAM3X8H__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@$(MAKE) CHIP=__SAM3X8H__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@ -8,7 +8,7 @@
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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# See the GNU Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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@ -51,6 +51,9 @@ CHIP_SERIE=sam3u
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else ifeq ($(CHIP), __SAM3N4C__)
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CHIP_NAME=sam3n4c
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CHIP_SERIE=sam3n
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else ifeq ($(CHIP), __SAM3X8E__)
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CHIP_NAME=sam3x8e
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CHIP_SERIE=sam3xa
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else ifeq ($(CHIP), __SAM3X8H__)
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CHIP_NAME=sam3x8h
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CHIP_SERIE=sam3xa
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@ -112,7 +115,7 @@ C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/source/templates/gcc/*.c)
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C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC)))
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# during development, remove some files
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C_OBJ_FILTER=pio_it.o adc.o
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C_OBJ_FILTER=
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C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
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@ -1,5 +1,5 @@
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011, Atmel Corporation
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*
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@ -73,51 +73,33 @@
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* Exported functions
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*----------------------------------------------------------------------------*/
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extern void PWMC_ConfigureChannel(
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Pwm* pPwm,
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uint8_t channel,
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uint32_t prescaler,
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uint32_t alignment,
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uint32_t polarity);
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extern void PWMC_ConfigureChannelExt(
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Pwm* pPwm,
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uint8_t channel,
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uint32_t prescaler,
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uint32_t alignment,
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uint32_t polarity,
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uint32_t countEventSelect,
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uint32_t DTEnable,
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uint32_t DTHInverte,
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uint32_t DTLInverte);
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extern void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck);
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extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period);
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extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty);
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extern void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL);
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extern void PWMC_ConfigureSyncChannel( Pwm* pPwm,
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uint32_t channels,
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uint32_t updateMode,
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uint32_t requestMode,
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uint32_t requestComparisonSelect);
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extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period);
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extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm );
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extern void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel);
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extern void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel);
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extern void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel);
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extern void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel);
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extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);
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extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);
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extern uint8_t PWMC_WriteBuffer(Pwm *pwmc,
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void *buffer,
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uint32_t length);
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extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value);
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extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);
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extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);
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extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode);
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extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault);
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extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value);
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extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value);
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extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode);
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extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode);
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extern void PWMC_ConfigureChannel( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity ) ;
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extern void PWMC_ConfigureChannelExt( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity,
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uint32_t countEventSelect, uint32_t DTEnable, uint32_t DTHInverte, uint32_t DTLInverte ) ;
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extern void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck ) ;
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extern void PWMC_SetPeriod( Pwm* pPwm, uint32_t ul_channel, uint16_t period ) ;
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extern void PWMC_SetDutyCycle( Pwm* pPwm, uint32_t ul_channel, uint16_t duty ) ;
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extern void PWMC_SetDeadTime( Pwm* pPwm, uint32_t ul_channel, uint16_t timeH, uint16_t timeL ) ;
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extern void PWMC_ConfigureSyncChannel( Pwm* pPwm, uint32_t ul_channels, uint32_t updateMode, uint32_t requestMode, uint32_t requestComparisonSelect ) ;
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extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period ) ;
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extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm ) ;
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extern void PWMC_EnableChannel( Pwm* pPwm, uint32_t ul_channel ) ;
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extern void PWMC_DisableChannel( Pwm* pPwm, uint32_t ul_channel ) ;
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extern void PWMC_EnableChannelIt( Pwm* pPwm, uint32_t ul_channel ) ;
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extern void PWMC_DisableChannelIt( Pwm* pPwm, uint32_t ul_channel ) ;
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extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2 ) ;
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extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2 ) ;
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extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, void *buffer, uint32_t length ) ;
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extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value ) ;
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extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync ) ;
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extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync ) ;
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extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode ) ;
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extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault ) ;
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extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value ) ;
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extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t ul_channel, uint32_t value ) ;
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extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode ) ;
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extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode ) ;
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#ifdef __cplusplus
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}
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@ -85,22 +85,13 @@
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part_is_defined( SAM3N4B ) || \
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part_is_defined( SAM3N4C ) )
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#define SAM3X2 ( \
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part_is_defined( SAM3X2C ) || \
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part_is_defined( SAM3X2E ) || \
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part_is_defined( SAM3X2G ) || \
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part_is_defined( SAM3X2H ) )
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#define SAM3X4 ( \
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part_is_defined( SAM3X4C ) || \
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part_is_defined( SAM3X4E ) || \
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part_is_defined( SAM3X4G ) || \
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part_is_defined( SAM3X4H ) )
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part_is_defined( SAM3X4E ) )
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#define SAM3X8 ( \
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part_is_defined( SAM3X8C ) || \
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part_is_defined( SAM3X8E ) || \
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part_is_defined( SAM3X8G ) || \
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part_is_defined( SAM3X8E ) || \
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part_is_defined( SAM3X8H ) )
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#define SAM3A2 ( \
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@ -122,7 +113,7 @@
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#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)
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/* Entire SAM3XA Family */
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#define SAM3XA (SAM3X2 || SAM3X4 || SAM3X8 || SAM3A2 || SAM3A4 || SAM3A8)
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#define SAM3XA ( SAM3X4 || SAM3X8 || SAM3A2 || SAM3A4 || SAM3A8)
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/* SAM9 family */
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@ -1,7 +1,7 @@
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011, Atmel Corporation
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* Copyright (c) 2012, Atmel Corporation
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*
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* All rights reserved.
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*
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@ -77,25 +77,32 @@
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#include "cmsis/sam3n/include/sam3n.h"
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#include "cmsis/sam3n/source/templates/system_sam3n.h"
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#include "cmsis/sam3n/source/templates/exceptions.h"
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#elif (defined __SAM3N0C__) || (defined __SAM3N0B__) || (defined __SAM3N0A__) /* SAM3N0 */
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#include "cmsis/sam3n/include/sam3n.h"
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#include "cmsis/sam3n/source/templates/system_sam3n.h"
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#include "cmsis/sam3n/source/templates/exceptions.h"
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#elif (defined __SAM3N00B__) || (defined __SAM3N00A__) /* SAM3N00 */
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#include "cmsis/sam3n/include/sam3n.h"
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#include "cmsis/sam3n/source/templates/system_sam3n.h"
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#include "cmsis/sam3n/source/templates/exceptions.h"
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#elif (defined __SAM3A8C__) || (defined __SAM3A4C__) || (defined __SAM3A2C__) /* SAM3A */
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#include "cmsis/sam3xa/include/sam3xa.h"
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#include "cmsis/sam3xa/source/templates/system_sam3xa.h"
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#include "cmsis/sam3xa/source/templates/exceptions.h"
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#elif (defined __SAM3X8C__) || (defined __SAM3X8E__) || (defined __SAM3X8G__) || (defined __SAM3X8H__) /* SAM3X8 */
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#elif (defined __SAM3X8C__) || (defined __SAM3X8E__) || (defined __SAM3X8H__) /* SAM3X8 */
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#include "cmsis/sam3xa/include/sam3xa.h"
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#include "cmsis/sam3xa/source/templates/system_sam3xa.h"
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#include "cmsis/sam3xa/source/templates/exceptions.h"
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#elif (defined __SAM3X4C__) || (defined __SAM3X4E__) || (defined __SAM3X4G__) || (defined __SAM3X4H__) /* SAM3X4 */
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#elif (defined __SAM3X4C__) || (defined __SAM3X4E__) /* SAM3X4 */
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#include "cmsis/sam3xa/include/sam3xa.h"
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#include "cmsis/sam3xa/source/templates/system_sam3xa.h"
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#include "cmsis/sam3xa/source/templates/exceptions.h"
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#elif (defined __SAM3X2C__) || (defined __SAM3X2E__) || (defined __SAM3X2G__) || (defined __SAM3X2H__) /* SAM3X2 */
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#elif (defined __SAM3A4C__) || (defined __SAM3A8C__) /* SAM3A */
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#include "cmsis/sam3xa/include/sam3xa.h"
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#include "cmsis/sam3xa/source/templates/system_sam3xa.h"
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#include "cmsis/sam3xa/source/templates/exceptions.h"
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#else
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#error Library does not support the specified device.
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#endif
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@ -1,5 +1,5 @@
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/* ----------------------------------------------------------------------------
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||||
* SAM Software Package License
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||||
* SAM Software Package License
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||||
* ----------------------------------------------------------------------------
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* Copyright (c) 2011, Atmel Corporation
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||||
*
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@ -34,14 +34,14 @@
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* The PWM macrocell controls square output waveforms of 4 channels.
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* Characteristics of output waveforms such as period, duty-cycle,
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* dead-time can be configured.\n
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* Some of PWM channels can be linked together as synchronous channel and
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* Some of PWM channels can be linked together as synchronous ul_channel and
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* duty-cycle of synchronous channels can be updated by PDC automaticly.
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*
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* Before enabling the channels, they must have been configured first.
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* The main settings include:
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* <ul>
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* <li>Configuration of the clock generator.</li>
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* <li>Selection of the clock for each channel.</li>
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* <li>Selection of the clock for each ul_channel.</li>
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||||
* <li>Configuration of output waveform characteristics, such as period, duty-cycle etc.</li>
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* <li>Configuration for synchronous channels if needed.</li>
|
||||
* - Selection of the synchronous channels.
|
||||
@ -54,7 +54,7 @@
|
||||
* After the channels is enabled, the user must use respective update registers
|
||||
* to change the wave characteristics to prevent unexpected output waveform.
|
||||
* i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle
|
||||
* when the channel is enabled.
|
||||
* when the ul_channel is enabled.
|
||||
*
|
||||
* For more accurate information, please look at the PWM section of the
|
||||
* Datasheet.
|
||||
@ -132,23 +132,18 @@ static uint16_t FindClockConfiguration(
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* \brief Configures PWM a channel with the given parameters, basic configure function.
|
||||
* \brief Configures PWM a ul_channel with the given parameters, basic configure function.
|
||||
*
|
||||
* The PWM controller must have been clocked in the PMC prior to calling this
|
||||
* function.
|
||||
* Beware: this function disables the channel. It waits until disable is effective.
|
||||
* Beware: this function disables the ul_channel. It waits until disable is effective.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
* \param prescaler Channel prescaler.
|
||||
* \param alignment Channel alignment.
|
||||
* \param polarity Channel polarity.
|
||||
*/
|
||||
void PWMC_ConfigureChannel(
|
||||
Pwm* pPwm,
|
||||
uint8_t channel,
|
||||
uint32_t prescaler,
|
||||
uint32_t alignment,
|
||||
uint32_t polarity)
|
||||
void PWMC_ConfigureChannel( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity )
|
||||
{
|
||||
pPwm->PWM_CH_NUM[0].PWM_CMR = 1;
|
||||
|
||||
@ -156,24 +151,24 @@ void PWMC_ConfigureChannel(
|
||||
assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
|
||||
assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
|
||||
|
||||
/* Disable channel (effective at the end of the current period) */
|
||||
if ((pPwm->PWM_SR & (1 << channel)) != 0) {
|
||||
pPwm->PWM_DIS = 1 << channel;
|
||||
while ((pPwm->PWM_SR & (1 << channel)) != 0);
|
||||
/* Disable ul_channel (effective at the end of the current period) */
|
||||
if ((pPwm->PWM_SR & (1 << ul_channel)) != 0) {
|
||||
pPwm->PWM_DIS = 1 << ul_channel;
|
||||
while ((pPwm->PWM_SR & (1 << ul_channel)) != 0);
|
||||
}
|
||||
|
||||
/* Configure channel */
|
||||
pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity;
|
||||
/* Configure ul_channel */
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_CMR = prescaler | alignment | polarity;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configures PWM a channel with the given parameters, extend configure function.
|
||||
* \brief Configures PWM a ul_channel with the given parameters, extend configure function.
|
||||
*
|
||||
* The PWM controller must have been clocked in the PMC prior to calling this
|
||||
* function.
|
||||
* Beware: this function disables the channel. It waits until disable is effective.
|
||||
* Beware: this function disables the ul_channel. It waits until disable is effective.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
* \param prescaler Channel prescaler.
|
||||
* \param alignment Channel alignment.
|
||||
* \param polarity Channel polarity.
|
||||
@ -182,16 +177,8 @@ void PWMC_ConfigureChannel(
|
||||
* \param DTHInverte Channel Dead-Time PWMHx output Inverted.
|
||||
* \param DTLInverte Channel Dead-Time PWMHx output Inverted.
|
||||
*/
|
||||
void PWMC_ConfigureChannelExt(
|
||||
Pwm* pPwm,
|
||||
uint8_t channel,
|
||||
uint32_t prescaler,
|
||||
uint32_t alignment,
|
||||
uint32_t polarity,
|
||||
uint32_t countEventSelect,
|
||||
uint32_t DTEnable,
|
||||
uint32_t DTHInverte,
|
||||
uint32_t DTLInverte)
|
||||
void PWMC_ConfigureChannelExt( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity,
|
||||
uint32_t countEventSelect, uint32_t DTEnable, uint32_t DTHInverte, uint32_t DTLInverte )
|
||||
{
|
||||
// assert(prescaler < PWM_CMR0_CPRE_MCKB);
|
||||
assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
|
||||
@ -201,14 +188,14 @@ void PWMC_ConfigureChannelExt(
|
||||
assert((DTHInverte & (uint32_t)~PWM_CMR_DTHI) == 0);
|
||||
assert((DTLInverte & (uint32_t)~PWM_CMR_DTLI) == 0);
|
||||
|
||||
/* Disable channel (effective at the end of the current period) */
|
||||
if ((pPwm->PWM_SR & (1 << channel)) != 0) {
|
||||
pPwm->PWM_DIS = 1 << channel;
|
||||
while ((pPwm->PWM_SR & (1 << channel)) != 0);
|
||||
/* Disable ul_channel (effective at the end of the current period) */
|
||||
if ((pPwm->PWM_SR & (1 << ul_channel)) != 0) {
|
||||
pPwm->PWM_DIS = 1 << ul_channel;
|
||||
while ((pPwm->PWM_SR & (1 << ul_channel)) != 0);
|
||||
}
|
||||
|
||||
/* Configure channel */
|
||||
pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity |
|
||||
/* Configure ul_channel */
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_CMR = prescaler | alignment | polarity |
|
||||
countEventSelect | DTEnable | DTHInverte | DTLInverte;
|
||||
}
|
||||
|
||||
@ -248,109 +235,105 @@ void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck)
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the period value used by a PWM channel.
|
||||
* \brief Sets the period value used by a PWM ul_channel.
|
||||
*
|
||||
* This function writes directly to the CPRD register if the channel is disabled;
|
||||
* This function writes directly to the CPRD register if the ul_channel is disabled;
|
||||
* otherwise, it uses the update register CPRDUPD.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
* \param period Period value.
|
||||
*/
|
||||
void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period)
|
||||
void PWMC_SetPeriod( Pwm* pPwm, uint32_t ul_channel, uint16_t period)
|
||||
{
|
||||
/* If channel is disabled, write to CPRD */
|
||||
if ((pPwm->PWM_SR & (1 << channel)) == 0) {
|
||||
/* If ul_channel is disabled, write to CPRD */
|
||||
if ((pPwm->PWM_SR & (1 << ul_channel)) == 0) {
|
||||
|
||||
pPwm->PWM_CH_NUM[channel].PWM_CPRD = period;
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD = period;
|
||||
}
|
||||
/* Otherwise use update register */
|
||||
else {
|
||||
|
||||
pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period;
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_CPRDUPD = period;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the duty cycle used by a PWM channel.
|
||||
* This function writes directly to the CDTY register if the channel is disabled;
|
||||
* \brief Sets the duty cycle used by a PWM ul_channel.
|
||||
* This function writes directly to the CDTY register if the ul_channel is disabled;
|
||||
* otherwise it uses the update register CDTYUPD.
|
||||
* Note that the duty cycle must always be inferior or equal to the channel
|
||||
* Note that the duty cycle must always be inferior or equal to the ul_channel
|
||||
* period.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
* \param duty Duty cycle value.
|
||||
*/
|
||||
void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty)
|
||||
void PWMC_SetDutyCycle( Pwm* pPwm, uint32_t ul_channel, uint16_t duty)
|
||||
{
|
||||
assert(duty <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
|
||||
assert(duty <= pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD);
|
||||
|
||||
/* If channel is disabled, write to CDTY */
|
||||
if ((pPwm->PWM_SR & (1 << channel)) == 0) {
|
||||
/* If ul_channel is disabled, write to CDTY */
|
||||
if ((pPwm->PWM_SR & (1 << ul_channel)) == 0) {
|
||||
|
||||
pPwm->PWM_CH_NUM[channel].PWM_CDTY = duty;
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_CDTY = duty;
|
||||
}
|
||||
/* Otherwise use update register */
|
||||
else {
|
||||
|
||||
pPwm->PWM_CH_NUM[channel].PWM_CDTYUPD = duty;
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_CDTYUPD = duty;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the dead time used by a PWM channel.
|
||||
* This function writes directly to the DT register if the channel is disabled;
|
||||
* \brief Sets the dead time used by a PWM ul_channel.
|
||||
* This function writes directly to the DT register if the ul_channel is disabled;
|
||||
* otherwise it uses the update register DTUPD.
|
||||
* Note that the dead time must always be inferior or equal to the channel
|
||||
* Note that the dead time must always be inferior or equal to the ul_channel
|
||||
* period.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
* \param timeH Dead time value for PWMHx output.
|
||||
* \param timeL Dead time value for PWMLx output.
|
||||
*/
|
||||
void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL)
|
||||
void PWMC_SetDeadTime( Pwm* pPwm, uint32_t ul_channel, uint16_t timeH, uint16_t timeL)
|
||||
{
|
||||
assert(timeH <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
|
||||
assert(timeL <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
|
||||
assert(timeH <= pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD);
|
||||
assert(timeL <= pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD);
|
||||
|
||||
/* If channel is disabled, write to DT */
|
||||
if ((pPwm->PWM_SR & (1 << channel)) == 0) {
|
||||
/* If ul_channel is disabled, write to DT */
|
||||
if ((pPwm->PWM_SR & (1 << ul_channel)) == 0) {
|
||||
|
||||
pPwm->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16);
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_DT = timeH | (timeL << 16);
|
||||
}
|
||||
/* Otherwise use update register */
|
||||
else {
|
||||
pPwm->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16);
|
||||
pPwm->PWM_CH_NUM[ul_channel].PWM_DTUPD = timeH | (timeL << 16);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configures Syncronous channel with the given parameters.
|
||||
* \brief Configures Syncronous ul_channel with the given parameters.
|
||||
* Beware: At this time, the channels should be disabled.
|
||||
*
|
||||
* \param channels Bitwise OR of Syncronous channels.
|
||||
* \param updateMode Syncronous channel update mode.
|
||||
* \param updateMode Syncronous ul_channel update mode.
|
||||
* \param requestMode PDC transfer request mode.
|
||||
* \param requestComparisonSelect PDC transfer request comparison selection.
|
||||
*/
|
||||
void PWMC_ConfigureSyncChannel( Pwm* pPwm,
|
||||
uint32_t channels,
|
||||
uint32_t updateMode,
|
||||
uint32_t requestMode,
|
||||
uint32_t requestComparisonSelect)
|
||||
void PWMC_ConfigureSyncChannel( Pwm* pPwm, uint32_t ul_channels, uint32_t updateMode, uint32_t requestMode, uint32_t requestComparisonSelect )
|
||||
{
|
||||
pPwm->PWM_SCM = channels | updateMode | requestMode | requestComparisonSelect;
|
||||
pPwm->PWM_SCM = ul_channels | updateMode | requestMode | requestComparisonSelect;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the update period of the synchronous channels.
|
||||
* This function writes directly to the SCUP register if the channel #0 is disabled;
|
||||
* This function writes directly to the SCUP register if the ul_channel #0 is disabled;
|
||||
* otherwise it uses the update register SCUPUPD.
|
||||
*
|
||||
* \param period update period.
|
||||
*/
|
||||
void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period)
|
||||
void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period )
|
||||
{
|
||||
/* If channel is disabled, write to SCUP */
|
||||
/* If ul_channel is disabled, write to SCUP */
|
||||
if ((pPwm->PWM_SR & (1 << 0)) == 0) {
|
||||
|
||||
pPwm->PWM_SCUP = period;
|
||||
@ -379,49 +362,49 @@ void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm )
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables the given PWM channel.
|
||||
* \brief Enables the given PWM ul_channel.
|
||||
*
|
||||
* This does NOT enable the corresponding pin;this must be done in the user code.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
*/
|
||||
void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel)
|
||||
void PWMC_EnableChannel( Pwm* pPwm, uint32_t ul_channel)
|
||||
{
|
||||
pPwm->PWM_ENA = 1 << channel;
|
||||
pPwm->PWM_ENA = 1 << ul_channel;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables the given PWM channel.
|
||||
* \brief Disables the given PWM ul_channel.
|
||||
*
|
||||
* Beware, channel will be effectively disabled at the end of the current period.
|
||||
* Application can check channel is disabled using the following wait loop:
|
||||
* while ((PWM->PWM_SR & (1 << channel)) != 0);
|
||||
* Beware, ul_channel will be effectively disabled at the end of the current period.
|
||||
* Application can check ul_channel is disabled using the following wait loop:
|
||||
* while ((PWM->PWM_SR & (1 << ul_channel)) != 0);
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
*/
|
||||
void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel)
|
||||
void PWMC_DisableChannel( Pwm* pPwm, uint32_t ul_channel)
|
||||
{
|
||||
pPwm->PWM_DIS = 1 << channel;
|
||||
pPwm->PWM_DIS = 1 << ul_channel;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables the period interrupt for the given PWM channel.
|
||||
* \brief Enables the period interrupt for the given PWM ul_channel.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
*/
|
||||
void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel)
|
||||
void PWMC_EnableChannelIt( Pwm* pPwm, uint32_t ul_channel)
|
||||
{
|
||||
pPwm->PWM_IER1 = 1 << channel;
|
||||
pPwm->PWM_IER1 = 1 << ul_channel;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables the period interrupt for the given PWM channel.
|
||||
* \brief Disables the period interrupt for the given PWM ul_channel.
|
||||
*
|
||||
* \param channel Channel number.
|
||||
* \param ul_channel Channel number.
|
||||
*/
|
||||
void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel)
|
||||
void PWMC_DisableChannelIt( Pwm* pPwm, uint32_t ul_channel)
|
||||
{
|
||||
pPwm->PWM_IDR1 = 1 << channel;
|
||||
pPwm->PWM_IDR1 = 1 << ul_channel;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -455,18 +438,16 @@ void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
|
||||
* Note: Duty cycle of syncronous channels can update by PDC
|
||||
* when the field UPDM (Update Mode) in the PWM_SCM register is set to 2.
|
||||
*
|
||||
* \param pwmc Pointer to an Pwm instance.
|
||||
* \param buffer Data buffer to send.
|
||||
* \param length Length of the data buffer.
|
||||
* \param pwmc Pointer to an Pwm instance.
|
||||
* \param pvBuffer Data buffer to send.
|
||||
* \param length Length of the data buffer.
|
||||
*/
|
||||
uint8_t PWMC_WriteBuffer(Pwm *pwmc,
|
||||
void *buffer,
|
||||
uint32_t length)
|
||||
uint8_t PWMC_WriteBuffer( Pwm *pwmc, void* pvBuffer, uint32_t length)
|
||||
{
|
||||
/* Check if first bank is free */
|
||||
if (pwmc->PWM_TCR == 0) {
|
||||
|
||||
pwmc->PWM_TPR = (uint32_t) buffer;
|
||||
pwmc->PWM_TPR = (uint32_t) pvBuffer;
|
||||
pwmc->PWM_TCR = length;
|
||||
pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN;
|
||||
return 1;
|
||||
@ -474,7 +455,7 @@ uint8_t PWMC_WriteBuffer(Pwm *pwmc,
|
||||
/* Check if second bank is free */
|
||||
else if (pwmc->PWM_TNCR == 0) {
|
||||
|
||||
pwmc->PWM_TNPR = (uint32_t) buffer;
|
||||
pwmc->PWM_TNPR = (uint32_t) pvBuffer;
|
||||
pwmc->PWM_TNCR = length;
|
||||
return 1;
|
||||
}
|
||||
@ -562,9 +543,38 @@ void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value)
|
||||
*
|
||||
* \param value Bitwise OR of FPEx[y].
|
||||
*/
|
||||
void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value)
|
||||
void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t ul_channel, uint32_t ul_value)
|
||||
{
|
||||
pPwm->PWM_FPE = value;
|
||||
/* Fault Protection Enable Register */
|
||||
uint32_t ul_fault_enable_reg = 0;
|
||||
|
||||
#if (SAM3XA)
|
||||
if (ul_channel < 4)
|
||||
{
|
||||
ul_channel *= 8;
|
||||
ul_fault_enable_reg = pPwm->PWM_FPE1;
|
||||
ul_fault_enable_reg &= ~(0xFF << ul_channel);
|
||||
ul_fault_enable_reg |= (ul_value << ul_channel);
|
||||
pPwm->PWM_FPE1 = ul_fault_enable_reg;
|
||||
}
|
||||
else
|
||||
{
|
||||
ul_channel -= 4;
|
||||
ul_channel *= 8;
|
||||
ul_fault_enable_reg = pPwm->PWM_FPE2;
|
||||
ul_fault_enable_reg &= ~(0xFF << ul_channel);
|
||||
ul_fault_enable_reg |= (ul_value << ul_channel);
|
||||
pPwm->PWM_FPE2 = ul_fault_enable_reg;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (SAM3U || SAM3S || SAM4S)
|
||||
ul_channel *= 8;
|
||||
ul_fault_enable_reg = pPwm->PWM_FPE;
|
||||
ul_fault_enable_reg &= ~(0xFF << ul_channel);
|
||||
ul_fault_enable_reg |= (ul_value << ul_channel);
|
||||
pPwm->PWM_FPE = ul_fault_enable_reg;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
@ -578,7 +588,7 @@ void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32
|
||||
{
|
||||
assert(x < 8);
|
||||
|
||||
/* If channel is disabled, write to CMPxM & CMPxV */
|
||||
/* If ul_channel is disabled, write to CMPxM & CMPxV */
|
||||
if ((pPwm->PWM_SR & (1 << 0)) == 0) {
|
||||
pPwm->PWM_CMP[x].PWM_CMPM = mode;
|
||||
pPwm->PWM_CMP[x].PWM_CMPV = value;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user