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Fixed flush so that it actually is sure to flush all outstanding data.
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@ -79,14 +79,12 @@ void UARTClass::end( void )
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// clear any received data
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// clear any received data
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_rx_buffer->_iHead = _rx_buffer->_iTail ;
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_rx_buffer->_iHead = _rx_buffer->_iTail ;
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while (_tx_buffer->_iHead != _tx_buffer->_iTail); //wait for transmit data to be sent
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// Wait for any outstanding data to be sent
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flush();
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// Disable UART interrupt in NVIC
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( _dwIrq ) ;
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NVIC_DisableIRQ( _dwIrq ) ;
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// Wait for any outstanding data to be sent
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flush();
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pmc_disable_periph_clk( _dwId ) ;
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pmc_disable_periph_clk( _dwId ) ;
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}
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}
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@ -134,6 +132,7 @@ int UARTClass::read( void )
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void UARTClass::flush( void )
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void UARTClass::flush( void )
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{
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{
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while (_tx_buffer->_iHead != _tx_buffer->_iTail); //wait for transmit data to be sent
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// Wait for transmission to complete
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// Wait for transmission to complete
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while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
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while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
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;
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;
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