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Code Issues Releases Activity

[SAM] updating libsam and CAN files

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This commit is contained in:
Thibaut VIARD 2013-01-27 15:52:28 +01:00
parent 3a3bf643f9
commit e8c57c4f18
10 changed files with 512 additions and 39 deletions
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129
hardware/arduino/sam/libraries/CAN/CAN.cpp Normal file
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@ -0,0 +1,129 @@
#include "CAN.h"
#include "sn65hvd234.h"
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
/* CAN0 Transceiver */
SSN65HVD234_Data gCanTransceiver0 ;
/* CAN1 Transceiver */
SSN65HVD234_Data gCanTransceiver1 ;
/* CAN0 Transfer */
SCanTransfer gCanTransfer0 ;
/* CAN1 Transfer */
SCanTransfer gCanTransfer1 ;
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
uint32_t CAN_InitShieldHardware( uint32_t )
{
// Initialize CAN0 pins
PIO_Configure(
g_APinDescription[PINS_CAN0].pPort,
g_APinDescription[PINS_CAN0].ulPinType,
g_APinDescription[PINS_CAN0].ulPin,
g_APinDescription[PINS_CAN0].ulPinConfiguration);
/* Initialize CAN0 Transceiver */
SN65HVD234_Init( &gCanTransceiver0 ) ;
SN65HVD234_SetRs( &gCanTransceiver0, PIOB, PIO_PB20 ) ;
SN65HVD234_SetEN( &gCanTransceiver0, PIOB, PIO_PB21 ) ;
/* Enable CAN0 Transceiver */
SN65HVD234_DisableLowPower( &gCanTransceiver0 ) ;
SN65HVD234_Enable( &gCanTransceiver0 ) ;
// Initialize CAN1 pins
PIO_Configure(
g_APinDescription[PINS_CAN1].pPort,
g_APinDescription[PINS_CAN1].ulPinType,
g_APinDescription[PINS_CAN1].ulPin,
g_APinDescription[PINS_CAN1].ulPinConfiguration);
/* Initialize CAN1 Transceiver */
SN65HVD234_Init( &gCanTransceiver1 ) ;
SN65HVD234_SetRs( &gCanTransceiver1, PIOE, PIO_PB15 ) ;
SN65HVD234_SetEN( &gCanTransceiver1, PIOE, PIO_PB16 ) ;
/* Enable CAN1 Transceiver */
SN65HVD234_DisableLowPower( &gCanTransceiver1 ) ;
SN65HVD234_Enable( &gCanTransceiver1 ) ;
}
uint32_t CAN_DeInitShieldHardware( uint32_t )
{
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Default interrupt handler for CAN 0.
*/
void CAN0_IrqHandler( void )
{
CAN_Handler( CAN0, &gCanTransfer0 ) ;
}
/**
* \brief Default interrupt handler for CAN 1.
*/
void CAN1_IrqHandler( void )
{
CAN_Handler( CAN1, &gCanTransfer1 ) ;
}
/**
* main function
*/
extern int main( void )
{
if ( ( CAN_Init( CAN0, BOARD_MCK, 1000, &gCanTransfer0 ) == 1 ) &&
( CAN_Init( CAN1, BOARD_MCK, 1000, &gCanTransfer1 ) == 1 ) )
{
puts( "CAN initialization complete."STRING_EOL ) ;
/* Run tests */
puts( "Press any key to start test"STRING_EOL ) ;
UART_GetChar() ;
_Test1() ;
puts( "Press any key to continue..."STRING_EOL ) ;
UART_GetChar() ;
_Test2() ;
puts( "Press any key to continue..."STRING_EOL ) ;
UART_GetChar() ;
_Test3() ;
puts( "Press any key to continue..."STRING_EOL ) ;
UART_GetChar() ;
_Test4() ;
/* Disable CAN0 Controller */
CAN_Disable(CAN0) ;
/* Disable CAN0 Transceiver */
SN65HVD234_EnableLowPower( &gCanTransceiver0 ) ;
SN65HVD234_Disable( &gCanTransceiver0 ) ;
/* Disable CAN1 Controller */
CAN_Disable(CAN1) ;
/* Disable CAN1 Transceiver */
SN65HVD234_EnableLowPower( &gCanTransceiver1 ) ;
SN65HVD234_Disable( &gCanTransceiver1 ) ;
puts( "End of all test"STRING_EOL ) ;
}
else
{
puts( "ERROR CAN initialisation (synchro)"STRING_EOL ) ;
}
return 0 ;
}

0
hardware/arduino/sam/libraries/CAN/CAN.h Normal file
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3
hardware/arduino/sam/system/libsam/chip.h
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@ -52,6 +52,7 @@
#include "include/pio.h"
#include "include/pmc.h"
#include "include/pwmc.h"
#include "include/rstc.h"
#include "include/rtc.h"
#include "include/rtt.h"
#include "include/spi.h"
@ -67,7 +68,7 @@
#if (SAM3XA_SERIES)
#include "include/can.h"
//#include "include/emac.h"
#include "include/emac.h"
#include "include/trng.h"
#include "include/uotghs_device.h"
#include "include/uotghs_host.h"

23
hardware/arduino/sam/system/libsam/include/can.h
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@ -116,33 +116,54 @@ typedef struct {
*/
uint32_t can_init(Can *p_can, uint32_t ul_mck, uint32_t ul_baudrate);
void can_enable(Can *p_can);
void can_disable(Can *p_can);
void can_disable_low_power_mode(Can *p_can);
void can_enable_low_power_mode(Can *p_can);
void can_disable_autobaud_listen_mode(Can *p_can);
void can_enable_autobaud_listen_mode(Can *p_can);
void can_disable_overload_frame(Can *p_can);
void can_enable_overload_frame(Can *p_can);
void can_set_timestamp_capture_point(Can *p_can, uint32_t ul_flag);
void can_disable_time_triggered_mode(Can *p_can);
void can_enable_time_triggered_mode(Can *p_can);
void can_disable_timer_freeze(Can *p_can);
void can_enable_timer_freeze(Can *p_can);
void can_disable_tx_repeat(Can *p_can);
void can_enable_tx_repeat(Can *p_can);
void can_set_rx_sync_stage(Can *p_can, uint32_t ul_stage);
void can_enable_interrupt(Can *p_can, uint32_t dw_mask);
void can_disable_interrupt(Can *p_can, uint32_t dw_mask);
uint32_t can_get_interrupt_mask(Can *p_can);
uint32_t can_get_status(Can *p_can);
uint32_t can_get_internal_timer_value(Can *p_can);
uint32_t can_get_timestamp_value(Can *p_can);
uint8_t can_get_tx_error_cnt(Can *p_can);
uint8_t can_get_rx_error_cnt(Can *p_can);
void can_reset_internal_timer(Can *p_can);
void can_global_send_transfer_cmd(Can *p_can, uint8_t uc_mask);
void can_global_send_abort_cmd(Can *p_can, uint8_t uc_mask);
/*
* Mailbox functions
*/
void can_mailbox_set_timemark(Can *p_can, uint8_t uc_index, uint16_t us_cnt);
uint32_t can_mailbox_get_status(Can *p_can, uint8_t uc_index);
void can_mailbox_send_transfer_cmd(Can *p_can, uint8_t uc_index);
@ -154,7 +175,7 @@ uint32_t can_mailbox_tx_remote_frame(Can *p_can, can_mb_conf_t *p_mailbox);
void can_reset_all_mailbox(Can *p_can);
// from wilfredo
void reset_mailbox_conf(can_mb_conf_t *p_mailbox);
uint32_t can_reset_mailbox_data(can_mb_conf_t *p_mailbox);
/** @} */

78
hardware/arduino/sam/system/libsam/include/rstc.h Normal file
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@ -0,0 +1,78 @@
/**
* \file
*
* \brief Reset Controller (RSTC) driver for SAM.
*
* Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef RSTC_H_INCLUDED
#define RSTC_H_INCLUDED
#include "../chip.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Definitions of Reset Controller Status */
/** Reset cause */
#define RSTC_GENERAL_RESET (0 << RSTC_SR_RSTTYP_Pos)
#define RSTC_BACKUP_RESET (1 << RSTC_SR_RSTTYP_Pos)
#define RSTC_WATCHDOG_RESET (2 << RSTC_SR_RSTTYP_Pos)
#define RSTC_SOFTWARE_RESET (3 << RSTC_SR_RSTTYP_Pos)
#define RSTC_USER_RESET (4 << RSTC_SR_RSTTYP_Pos)
/** NRST Pin Level */
#define RSTC_NRST_LOW (LOW << 16)
#define RSTC_NRST_HIGH (HIGH << 16)
void rstc_set_external_reset(Rstc* p_rstc, const uint32_t ul_length);
void rstc_enable_user_reset(Rstc* p_rstc);
void rstc_disable_user_reset(Rstc* p_rstc);
void rstc_enable_user_reset_interrupt(Rstc* p_rstc);
void rstc_disable_user_reset_interrupt(Rstc* p_rstc);
void rstc_start_software_reset(Rstc* p_rstc);
void rstc_reset_extern(Rstc *p_rstc);
uint32_t rstc_get_status(Rstc* p_rstc);
uint32_t rstc_get_reset_cause(Rstc* p_rstc);
#ifdef __cplusplus
}
#endif
#endif /* RSTC_H_INCLUDED */

14
hardware/arduino/sam/system/libsam/source/can.c
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@ -42,6 +42,7 @@
*/
#include "../chip.h"
#include <string.h>
/// @cond 0
/**INDENT-OFF**/
@ -765,8 +766,14 @@ void can_reset_all_mailbox(Can *p_can)
}
// from wilfredo
void reset_mailbox_conf(can_mb_conf_t *p_mailbox)
uint32_t can_reset_mailbox_data(can_mb_conf_t *p_mailbox)
{
if ( p_mailbox == NULL )
{
return 1U ;
}
#if 0
p_mailbox->ul_mb_idx = 0;
p_mailbox->uc_obj_type = 0;
p_mailbox->uc_id_ver = 0;
@ -778,6 +785,11 @@ void reset_mailbox_conf(can_mb_conf_t *p_mailbox)
p_mailbox->ul_fid = 0;
p_mailbox->ul_datal = 0;
p_mailbox->ul_datah = 0;
#else
memset( p_mailbox, 0, sizeof( can_mb_conf_t ) ) ;
#endif
return 0U ;
}
#endif // SAM3XA_SERIES

13
hardware/arduino/sam/system/libsam/source/emac.c.disabled → hardware/arduino/sam/system/libsam/source/emac.c
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@ -42,7 +42,7 @@
*/
#include "../chip.h"
//#include <string.h>
#include <string.h>
/// @cond 0
/**INDENT-OFF**/
@ -69,6 +69,11 @@ extern "C" {
* @{
*/
#define EMAC_RX_BUFFERS 16
#define EMAC_TX_BUFFERS 8
#define MAC_PHY_RETRY_MAX 1000000
/** TX descriptor lists */
#ifdef __ICCARM__ /* IAR */
#pragma data_alignment=8
@ -283,9 +288,9 @@ static uint8_t emac_init_mem(Emac* p_emac, emac_device_t* p_emac_dev,
emac_reset_tx_mem(p_emac_dev);
/* Enable Rx and Tx, plus the statistics register */
emac_enable_transmit(p_emac, true);
emac_enable_receive(p_emac, true);
emac_enable_statistics_write(p_emac, true);
emac_enable_transmit(p_emac, 1);
emac_enable_receive(p_emac, 1);
emac_enable_statistics_write(p_emac, 1);
/* Set up the interrupts for transmission and errors */
emac_enable_interrupt(p_emac,

193
hardware/arduino/sam/system/libsam/source/rstc.c Normal file
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@ -0,0 +1,193 @@
/**
* \file
*
* \brief Reset Controller (RSTC) driver for SAM.
*
* Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "rstc.h"
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond
/**
* \defgroup sam_drivers_rstc_group Reset Controller (RSTC)
*
* Driver for the RSTC (Reset Controller). This driver provides access to the main
* features of the Reset controller.
*
* @{
*/
#define RSTC_KEY 0xA5000000
/**
* \brief Set external reset length.
*
* \param p_rstc Pointer to an RSTC instance.
* \param ul_length The length of external reset.
*/
void rstc_set_external_reset(Rstc *p_rstc, const uint32_t ul_length)
{
uint32_t mode = p_rstc->RSTC_MR;
mode &= ~(RSTC_MR_ERSTL_Msk | RSTC_MR_KEY_Msk);
mode |= (RSTC_MR_ERSTL(ul_length) | RSTC_KEY);
p_rstc->RSTC_MR = mode;
}
/**
* \brief Enable user reset.
*
* \param p_rstc Pointer to an RSTC instance.
*/
void rstc_enable_user_reset(Rstc *p_rstc)
{
uint32_t mode = p_rstc->RSTC_MR;
mode &= ~RSTC_MR_KEY_Msk;
mode |= (RSTC_MR_URSTEN | RSTC_KEY);
p_rstc->RSTC_MR = mode;
}
/**
* \brief Disable user reset.
*
* \param p_rstc Pointer to an RSTC instance.
*/
void rstc_disable_user_reset(Rstc *p_rstc)
{
uint32_t mode = p_rstc->RSTC_MR;
mode &= ~(RSTC_MR_URSTEN | RSTC_MR_KEY_Msk);
mode |= RSTC_KEY;
p_rstc->RSTC_MR = mode;
}
/**
* \brief Enable user reset interrupt.
*
* \param p_rstc Pointer to an RSTC instance.
*/
void rstc_enable_user_reset_interrupt(Rstc *p_rstc)
{
uint32_t mode = p_rstc->RSTC_MR;
mode &= ~RSTC_MR_KEY_Msk;
mode |= (RSTC_MR_URSTIEN | RSTC_KEY);
p_rstc->RSTC_MR = mode;
}
/**
* \brief Disable user reset interrupt.
*
* \param p_rstc Pointer to an RSTC instance.
*/
void rstc_disable_user_reset_interrupt(Rstc *p_rstc)
{
uint32_t mode = p_rstc->RSTC_MR;
mode &= ~(RSTC_MR_URSTIEN | RSTC_MR_KEY_Msk);
mode |= RSTC_KEY;
p_rstc->RSTC_MR = mode;
}
/**
* \brief Perform software reset.
*
* \param p_rstc Pointer to an RSTC instance.
*/
void rstc_start_software_reset(Rstc *p_rstc)
{
p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_PROCRST | RSTC_CR_PERRST;
}
/**
* \brief Asserts the NRST pin for external resets.
*
* \param p_rstc Pointer to an RSTC instance.
*/
void rstc_reset_extern(Rstc *p_rstc)
{
p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_EXTRST;
}
/**
* \brief Get RSTC status.
*
* \param p_rstc Pointer to an RSTC instance.
*
* \return RSTC status.
*/
uint32_t rstc_get_status(Rstc *p_rstc)
{
return p_rstc->RSTC_SR;
}
/**
* \brief Get reset cause.
*
* \param p_rstc Pointer to an RSTC instance.
*
* \return The last reset cause.
*/
uint32_t rstc_get_reset_cause(Rstc *p_rstc)
{
return (p_rstc->RSTC_SR & RSTC_SR_RSTTYP_Msk);
}
//@}
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond

BIN
hardware/arduino/sam/variants/arduino_due_x/libsam_sam3x8e_gcc_rel.a
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Binary file not shown.

98
hardware/arduino/sam/variants/arduino_due_x/libsam_sam3x8e_gcc_rel.a.txt
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@ -99,14 +99,14 @@ pwmc.o:
00000000 T PWMC_SetSyncChannelUpdateUnlock
00000000 T PWMC_WriteBuffer
U __assert_func
00000000 r __func__.6271
00000000 r __func__.6282
00000000 r __func__.6297
00000000 r __func__.6308
00000000 r __func__.6319
00000000 r __func__.6326
00000000 r __func__.6410
00000000 r __func__.6416
00000000 r __func__.6766
00000000 r __func__.6777
00000000 r __func__.6792
00000000 r __func__.6803
00000000 r __func__.6814
00000000 r __func__.6821
00000000 r __func__.6905
00000000 r __func__.6911
rtc.o:
00000000 T RTC_ClearSCCR
@ -122,9 +122,9 @@ rtc.o:
00000000 T RTC_SetTime
00000000 T RTC_SetTimeAlarm
U __assert_func
00000000 r __func__.6268
00000000 r __func__.6277
00000000 r __func__.6282
00000000 r __func__.6763
00000000 r __func__.6772
00000000 r __func__.6777
rtt.o:
00000000 T RTT_EnableIT
@ -133,8 +133,8 @@ rtt.o:
00000000 T RTT_SetAlarm
00000000 T RTT_SetPrescaler
U __assert_func
00000000 r __func__.6275
00000000 r __func__.6283
00000000 r __func__.6770
00000000 r __func__.6778
spi.o:
00000000 T SPI_Configure
@ -160,9 +160,9 @@ tc.o:
00000000 T TC_Start
00000000 T TC_Stop
U __assert_func
00000000 r __func__.6270
00000000 r __func__.6276
00000000 r __func__.6282
00000000 r __func__.6765
00000000 r __func__.6771
00000000 r __func__.6777
timetick.o:
00000000 T GetTickCount
@ -189,18 +189,18 @@ twi.o:
00000000 T TWI_TransferComplete
00000000 T TWI_WriteByte
U __assert_func
00000000 r __func__.6635
00000000 r __func__.6650
00000000 r __func__.6654
00000000 r __func__.6661
00000000 r __func__.6665
00000000 r __func__.6670
00000000 r __func__.6678
00000000 r __func__.6692
00000000 r __func__.6697
00000000 r __func__.6701
00000000 r __func__.6706
00000000 r __func__.6710
00000000 r __func__.7130
00000000 r __func__.7145
00000000 r __func__.7149
00000000 r __func__.7156
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00000000 r __func__.7173
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00000000 r __func__.7192
00000000 r __func__.7196
00000000 r __func__.7201
00000000 r __func__.7205
usart.o:
00000000 T USART_Configure
@ -219,7 +219,7 @@ usart.o:
00000000 T USART_Write
00000000 T USART_WriteBuffer
U __assert_func
00000000 r __func__.6556
00000000 r __func__.7051
wdt.o:
00000000 T WDT_Disable
@ -467,8 +467,10 @@ can.o:
00000000 T can_mailbox_write
00000000 T can_reset_all_mailbox
00000000 T can_reset_internal_timer
00000000 T can_reset_mailbox_data
00000000 T can_set_rx_sync_stage
00000000 T can_set_timestamp_capture_point
U memset
efc.o:
00000000 T efc_disable_frdy_interrupt
@ -479,12 +481,12 @@ efc.o:
00000000 T efc_get_wait_state
00000000 T efc_init
00000000 T efc_perform_command
0000006c T efc_perform_fcr
00000068 T efc_perform_fcr
00000000 T efc_perform_read_sequence
00000000 T efc_set_flash_access_mode
00000000 T efc_set_wait_state
00000068 T efc_write_fmr
00000000 b iap_perform_command.6537
00000064 T efc_write_fmr
00000000 b iap_perform_command.7032
gpbr.o:
00000000 T gpbr_read
@ -536,3 +538,35 @@ trng.o:
00000000 T trng_get_interrupt_mask
00000000 T trng_get_interrupt_status
00000000 T trng_read_output_data
rstc.o:
00000000 T rstc_disable_user_reset
00000000 T rstc_disable_user_reset_interrupt
00000000 T rstc_enable_user_reset
00000000 T rstc_enable_user_reset_interrupt
00000000 T rstc_get_reset_cause
00000000 T rstc_get_status
00000000 T rstc_reset_extern
00000000 T rstc_set_external_reset
00000000 T rstc_start_software_reset
emac.o:
00000000 t circ_inc
00000000 T emac_dev_get_tx_load
00000000 T emac_dev_init
00000000 T emac_dev_read
00000000 T emac_dev_reset
00000000 T emac_dev_set_rx_callback
00000000 T emac_dev_set_tx_wakeup_callback
00000000 T emac_dev_write
00000000 T emac_handler
00000000 T emac_phy_read
00000000 T emac_phy_write
00000000 t emac_reset_rx_mem
00000000 t emac_reset_tx_mem
00000000 b gs_rx_desc
00000000 b gs_tx_callback
00000000 b gs_tx_desc
00000000 b gs_uc_rx_buffer
00000000 b gs_uc_tx_buffer
U memcpy