/* %ATMEL_LICENCE% */

#ifndef _SAM3XA_PIOE_INSTANCE_
#define _SAM3XA_PIOE_INSTANCE_

/* ========== Register definition for PIOE peripheral ========== */
#define REG_PIOE_PER    REG_ACCESS(WoReg, 0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
#define REG_PIOE_PDR    REG_ACCESS(WoReg, 0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
#define REG_PIOE_PSR    REG_ACCESS(RoReg, 0x400E1608U) /**< \brief (PIOE) PIO Status Register */
#define REG_PIOE_OER    REG_ACCESS(WoReg, 0x400E1610U) /**< \brief (PIOE) Output Enable Register */
#define REG_PIOE_ODR    REG_ACCESS(WoReg, 0x400E1614U) /**< \brief (PIOE) Output Disable Register */
#define REG_PIOE_OSR    REG_ACCESS(RoReg, 0x400E1618U) /**< \brief (PIOE) Output Status Register */
#define REG_PIOE_IFER   REG_ACCESS(WoReg, 0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR   REG_ACCESS(WoReg, 0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR   REG_ACCESS(RoReg, 0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR   REG_ACCESS(WoReg, 0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
#define REG_PIOE_CODR   REG_ACCESS(WoReg, 0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR   REG_ACCESS(RwReg, 0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR   REG_ACCESS(RoReg, 0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
#define REG_PIOE_IER    REG_ACCESS(WoReg, 0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR    REG_ACCESS(WoReg, 0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR    REG_ACCESS(RoReg, 0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR    REG_ACCESS(RoReg, 0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER   REG_ACCESS(WoReg, 0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR   REG_ACCESS(WoReg, 0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR   REG_ACCESS(RoReg, 0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR   REG_ACCESS(WoReg, 0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER   REG_ACCESS(WoReg, 0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR   REG_ACCESS(RoReg, 0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABSR   REG_ACCESS(RwReg, 0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
#define REG_PIOE_SCIFSR REG_ACCESS(WoReg, 0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
#define REG_PIOE_DIFSR  REG_ACCESS(WoReg, 0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
#define REG_PIOE_IFDGSR REG_ACCESS(RoReg, 0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
#define REG_PIOE_SCDR   REG_ACCESS(RwReg, 0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_OWER   REG_ACCESS(WoReg, 0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
#define REG_PIOE_OWDR   REG_ACCESS(WoReg, 0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
#define REG_PIOE_OWSR   REG_ACCESS(RoReg, 0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER  REG_ACCESS(WoReg, 0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR  REG_ACCESS(WoReg, 0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
#define REG_PIOE_AIMMR  REG_ACCESS(RoReg, 0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR    REG_ACCESS(WoReg, 0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
#define REG_PIOE_LSR    REG_ACCESS(WoReg, 0x400E16C4U) /**< \brief (PIOE) Level Select Register */
#define REG_PIOE_ELSR   REG_ACCESS(RoReg, 0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR REG_ACCESS(WoReg, 0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
#define REG_PIOE_REHLSR REG_ACCESS(WoReg, 0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
#define REG_PIOE_FRLHSR REG_ACCESS(RoReg, 0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR REG_ACCESS(RoReg, 0x400E16E0U) /**< \brief (PIOE) Lock Status */
#define REG_PIOE_WPMR   REG_ACCESS(RwReg, 0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
#define REG_PIOE_WPSR   REG_ACCESS(RoReg, 0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */

#endif /* _SAM3XA_PIOE_INSTANCE_ */