/* $asf_license$ */ #ifndef _SAM3S8_EFC_COMPONENT_ #define _SAM3S8_EFC_COMPONENT_ /* ============================================================================= */ /** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ /* ============================================================================= */ /** \addtogroup SAM3S8_EFC Embedded Flash Controller */ /*@{*/ #ifndef __ASSEMBLY__ /** \brief Efc hardware registers */ typedef struct { RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ } Efc; #endif /* __ASSEMBLY__ */ /* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ #define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ #define EEFC_FMR_FWS_Pos 8 #define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ #define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) #define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ #define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ /* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ #define EEFC_FCR_FCMD_Pos 0 #define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ #define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) #define EEFC_FCR_FARG_Pos 8 #define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ #define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) #define EEFC_FCR_FKEY_Pos 24 #define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ #define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) /* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ #define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ #define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ #define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ /* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ #define EEFC_FRR_FVALUE_Pos 0 #define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ /*@}*/ #endif /* _SAM3S8_EFC_COMPONENT_ */