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https://github.com/arduino/Arduino.git
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287 lines
14 KiB
C
287 lines
14 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3S1A_
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#define _SAM3S1A_
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/** \addtogroup SAM3S1A_definitions SAM3S1A definitions
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This file defines all structures and symbols for SAM3S1A:
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- registers and bitfields
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- peripheral base address
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- peripheral ID
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- PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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#define CAST(type, value) (((type)*)(value))
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#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
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#else
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#define CAST(type, value) (value)
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#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
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#endif
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/* ************************************************************************** */
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/* CMSIS DEFINITIONS FOR SAM3S1A */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1A_cmsis CMSIS Definitions */
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/*@{*/
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/**< Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ******************************/
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
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/****** SAM3S1A specific Interrupt Numbers *********************************/
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SUPC_IRQn = 0, /**< 0 SAM3S1A Supply Controller (SUPC) */
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RSTC_IRQn = 1, /**< 1 SAM3S1A Reset Controller (RSTC) */
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RTC_IRQn = 2, /**< 2 SAM3S1A Real Time Clock (RTC) */
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RTT_IRQn = 3, /**< 3 SAM3S1A Real Time Timer (RTT) */
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WDT_IRQn = 4, /**< 4 SAM3S1A Watchdog Timer (WDT) */
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PMC_IRQn = 5, /**< 5 SAM3S1A Power Management Controller (PMC) */
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EFC_IRQn = 6, /**< 6 SAM3S1A Enhanced Embedded Flash Controller (EFC) */
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UART0_IRQn = 8, /**< 8 SAM3S1A UART 0 (UART0) */
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UART1_IRQn = 9, /**< 9 SAM3S1A UART 1 (UART1) */
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SMC_IRQn = 10, /**< 10 SAM3S1A Static Memory Controller (SMC) */
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PIOA_IRQn = 11, /**< 11 SAM3S1A Parallel I/O Controller A (PIOA) */
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PIOB_IRQn = 12, /**< 12 SAM3S1A Parallel I/O Controller B (PIOB) */
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PIOC_IRQn = 13, /**< 13 SAM3S1A Parallel I/O Controller C (PIOC) */
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USART0_IRQn = 14, /**< 14 SAM3S1A USART 0 (USART0) */
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USART1_IRQn = 15, /**< 15 SAM3S1A USART 1 (USART1) */
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HSMCI_IRQn = 18, /**< 18 SAM3S1A Multimedia Card Interface (HSMCI) */
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TWI0_IRQn = 19, /**< 19 SAM3S1A Two Wire Interface 0 (TWI0) */
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TWI1_IRQn = 20, /**< 20 SAM3S1A Two Wire Interface 1 (TWI1) */
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SPI_IRQn = 21, /**< 21 SAM3S1A Serial Peripheral Interface (SPI) */
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SSC_IRQn = 22, /**< 22 SAM3S1A Synchronous Serial Controler (SSC) */
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TC0_IRQn = 23, /**< 23 SAM3S1A Timer/Counter 0 (TC0) */
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TC1_IRQn = 24, /**< 24 SAM3S1A Timer/Counter 1 (TC1) */
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TC2_IRQn = 25, /**< 25 SAM3S1A Timer/Counter 2 (TC2) */
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TC3_IRQn = 26, /**< 26 SAM3S1A Timer/Counter 3 (TC3) */
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TC4_IRQn = 27, /**< 27 SAM3S1A Timer/Counter 4 (TC4) */
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TC5_IRQn = 28, /**< 28 SAM3S1A Timer/Counter 5 (TC5) */
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ADC_IRQn = 29, /**< 29 SAM3S1A Analog To Digital Converter (ADC) */
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DACC_IRQn = 30, /**< 30 SAM3S1A Digital To Analog Converter (DACC) */
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PWM_IRQn = 31, /**< 31 SAM3S1A Pulse Width Modulation (PWM) */
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CRCCU_IRQn = 32, /**< 32 SAM3S1A CRC Calculation Unit (CRCCU) */
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ACC_IRQn = 33, /**< 33 SAM3S1A Analog Comparator (ACC) */
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UDP_IRQn = 34 /**< 34 SAM3S1A USB Device Port (UDP) */
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} IRQn_Type;
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/**
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* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#define __MPU_PRESENT 1 /**< SAM3S1A does provide a MPU */
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#define __NVIC_PRIO_BITS 4 /**< SAM3S1A uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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/*
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* \brief CMSIS includes
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*/
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#include <core_cm3.h>
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1A */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1A_api Peripheral Software API */
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/*@{*/
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#include "component/ACC.h"
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#include "component/ADC.h"
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#include "component/CHIPID.h"
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#include "component/CRCCU.h"
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#include "component/EFC.h"
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#include "component/GPBR.h"
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#include "component/MATRIX.h"
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#include "component/PDC.h"
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#include "component/PIO.h"
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#include "component/PMC.h"
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#include "component/PWM.h"
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#include "component/RSTC.h"
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#include "component/RTC.h"
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#include "component/RTT.h"
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#include "component/SPI.h"
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#include "component/SSC.h"
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#include "component/SUPC.h"
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#include "component/TC.h"
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#include "component/TWI.h"
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#include "component/UART.h"
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#include "component/UDP.h"
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#include "component/USART.h"
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#include "component/WDT.h"
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/*@}*/
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/* ************************************************************************** */
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/* REGISTER ACCESS DEFINITIONS FOR SAM3S1A */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1A_reg Registers Access Definitions */
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/*@{*/
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#include "instance/SSC.h"
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#include "instance/SPI.h"
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#include "instance/TC0.h"
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#include "instance/TWI0.h"
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#include "instance/TWI1.h"
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#include "instance/PWM.h"
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#include "instance/USART0.h"
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#include "instance/UDP.h"
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#include "instance/ADC.h"
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#include "instance/ACC.h"
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#include "instance/CRCCU.h"
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#include "instance/MATRIX.h"
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#include "instance/PMC.h"
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#include "instance/UART0.h"
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#include "instance/CHIPID.h"
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#include "instance/UART1.h"
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#include "instance/EFC.h"
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#include "instance/PIOA.h"
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#include "instance/PIOB.h"
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#include "instance/RSTC.h"
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#include "instance/SUPC.h"
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#include "instance/RTT.h"
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#include "instance/WDT.h"
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#include "instance/RTC.h"
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#include "instance/GPBR.h"
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/*@}*/
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/* ************************************************************************** */
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/* PERIPHERAL ID DEFINITIONS FOR SAM3S1A */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1A_id Peripheral Ids Definitions */
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/*@{*/
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#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
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#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
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#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
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#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
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#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
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#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
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#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
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#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
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#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
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#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */
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#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
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#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
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#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
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#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
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#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
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#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
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#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
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#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
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#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
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#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */
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#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
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#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
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#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
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#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
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#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
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#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
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#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
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#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
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#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
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#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */
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#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
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#define ID_UDP (34) /**< \brief USB Device Port (UDP) */
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/*@}*/
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/* ************************************************************************** */
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/* BASE ADDRESS DEFINITIONS FOR SAM3S1A */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1A_base Peripheral Base Address Definitions */
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/*@{*/
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#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
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#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */
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#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
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#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
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#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
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#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
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#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
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#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
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#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */
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#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
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#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */
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#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
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#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
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#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */
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#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
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#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
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#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */
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#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */
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#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
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#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
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#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
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#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
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#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
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#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
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#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
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#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
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#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
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#define PDC_PIOA CAST(Pdc , 0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */
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#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
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#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
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#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
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#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
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#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
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#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
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#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
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/*@}*/
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/* ************************************************************************** */
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/* PIO DEFINITIONS FOR SAM3S1A */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1A_pio Peripheral Pio Definitions */
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/*@{*/
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#include "pio/SAM3S1A.h"
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/*@}*/
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/* ************************************************************************** */
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/* MEMORY MAPPING DEFINITIONS FOR SAM3S1A */
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/* ************************************************************************** */
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#define IFLASH_SIZE 0x10000
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#define IFLASH_PAGE_SIZE 256
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#define IFLASH_LOCK_REGION_SIZE 16384
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#define IFLASH_NB_OF_PAGES 256
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#define IFLASH_NB_OF_LOCK_BITS 4
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#define IRAM_SIZE 0x4000
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#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
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#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
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#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
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#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
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#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
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#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
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#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif /* _SAM3S1A_ */
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