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72 lines
4.6 KiB
C
72 lines
4.6 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3XA_PDC_COMPONENT_
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#define _SAM3XA_PDC_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
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/* ============================================================================= */
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/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */
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/*@{*/
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#ifndef __ASSEMBLY__
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/** \brief Pdc hardware registers */
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typedef struct {
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RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
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RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
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RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
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RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
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RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
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RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
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RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
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RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
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WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
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RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
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} Pdc;
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#endif /* __ASSEMBLY__ */
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/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
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#define PERIPH_RPR_RXPTR_Pos 0
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#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
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#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
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/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
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#define PERIPH_RCR_RXCTR_Pos 0
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#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
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#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
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/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
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#define PERIPH_TPR_TXPTR_Pos 0
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#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
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#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
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/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
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#define PERIPH_TCR_TXCTR_Pos 0
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#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
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#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
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/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
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#define PERIPH_RNPR_RXNPTR_Pos 0
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#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
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#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
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/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
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#define PERIPH_RNCR_RXNCTR_Pos 0
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#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
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#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
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/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
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#define PERIPH_TNPR_TXNPTR_Pos 0
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#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
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#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
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/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
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#define PERIPH_TNCR_TXNCTR_Pos 0
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#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
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#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
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/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
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#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
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#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
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#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
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#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
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/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
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#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
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#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
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/*@}*/
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#endif /* _SAM3XA_PDC_COMPONENT_ */
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