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47 lines
2.2 KiB
C
47 lines
2.2 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3XA_RSTC_COMPONENT_
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#define _SAM3XA_RSTC_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR Reset Controller */
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/* ============================================================================= */
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/** \addtogroup SAM3XA_RSTC Reset Controller */
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/*@{*/
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#ifndef __ASSEMBLY__
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/** \brief Rstc hardware registers */
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typedef struct {
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WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
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RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
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RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
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} Rstc;
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#endif /* __ASSEMBLY__ */
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/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
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#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
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#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
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#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
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#define RSTC_CR_KEY_Pos 24
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#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
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#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
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/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
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#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
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#define RSTC_SR_RSTTYP_Pos 8
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#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
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#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
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#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
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/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
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#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
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#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
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#define RSTC_MR_ERSTL_Pos 8
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#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
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#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
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#define RSTC_MR_KEY_Pos 24
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#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
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#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
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/*@}*/
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#endif /* _SAM3XA_RSTC_COMPONENT_ */
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