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82 lines
7.9 KiB
C
82 lines
7.9 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3XA_SMC_INSTANCE_
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#define _SAM3XA_SMC_INSTANCE_
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/* ========== Register definition for SMC peripheral ========== */
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#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
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#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
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#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
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#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
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#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
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#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
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#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
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#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
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#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
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#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
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#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
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#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
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#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
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#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
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#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
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#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
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#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
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#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
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#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
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#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
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#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
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#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
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#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
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#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
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#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
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#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
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#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
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#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
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#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
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#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
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#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
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#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
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#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
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#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
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#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
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#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
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#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
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#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
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#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
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#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
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#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
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#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
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#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
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#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
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#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
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#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
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#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
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#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
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#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
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#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
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#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
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#define REG_SMC_TIMINGS4 REG_ACCESS(RwReg, 0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */
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#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
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#define REG_SMC_SETUP5 REG_ACCESS(RwReg, 0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */
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#define REG_SMC_PULSE5 REG_ACCESS(RwReg, 0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */
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#define REG_SMC_CYCLE5 REG_ACCESS(RwReg, 0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */
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#define REG_SMC_TIMINGS5 REG_ACCESS(RwReg, 0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */
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#define REG_SMC_MODE5 REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */
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#define REG_SMC_SETUP6 REG_ACCESS(RwReg, 0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */
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#define REG_SMC_PULSE6 REG_ACCESS(RwReg, 0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */
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#define REG_SMC_CYCLE6 REG_ACCESS(RwReg, 0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */
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#define REG_SMC_TIMINGS6 REG_ACCESS(RwReg, 0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */
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#define REG_SMC_MODE6 REG_ACCESS(RwReg, 0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */
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#define REG_SMC_SETUP7 REG_ACCESS(RwReg, 0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */
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#define REG_SMC_PULSE7 REG_ACCESS(RwReg, 0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */
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#define REG_SMC_CYCLE7 REG_ACCESS(RwReg, 0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */
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#define REG_SMC_TIMINGS7 REG_ACCESS(RwReg, 0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */
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#define REG_SMC_MODE7 REG_ACCESS(RwReg, 0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */
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#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
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#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
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#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
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#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
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#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
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#endif /* _SAM3XA_SMC_INSTANCE_ */
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