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20 lines
1.3 KiB
C
20 lines
1.3 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3XA_SPI0_INSTANCE_
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#define _SAM3XA_SPI0_INSTANCE_
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/* ========== Register definition for SPI0 peripheral ========== */
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#define REG_SPI0_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI0) Control Register */
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#define REG_SPI0_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI0) Mode Register */
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#define REG_SPI0_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI0) Receive Data Register */
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#define REG_SPI0_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
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#define REG_SPI0_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI0) Status Register */
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#define REG_SPI0_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
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#define REG_SPI0_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
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#define REG_SPI0_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
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#define REG_SPI0_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI0) Chip Select Register */
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#define REG_SPI0_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
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#define REG_SPI0_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
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#endif /* _SAM3XA_SPI0_INSTANCE_ */
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