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20 lines
1.3 KiB
C
20 lines
1.3 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3XA_SPI1_INSTANCE_
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#define _SAM3XA_SPI1_INSTANCE_
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/* ========== Register definition for SPI1 peripheral ========== */
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#define REG_SPI1_CR REG_ACCESS(WoReg, 0x4000C000U) /**< \brief (SPI1) Control Register */
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#define REG_SPI1_MR REG_ACCESS(RwReg, 0x4000C004U) /**< \brief (SPI1) Mode Register */
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#define REG_SPI1_RDR REG_ACCESS(RoReg, 0x4000C008U) /**< \brief (SPI1) Receive Data Register */
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#define REG_SPI1_TDR REG_ACCESS(WoReg, 0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
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#define REG_SPI1_SR REG_ACCESS(RoReg, 0x4000C010U) /**< \brief (SPI1) Status Register */
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#define REG_SPI1_IER REG_ACCESS(WoReg, 0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
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#define REG_SPI1_IDR REG_ACCESS(WoReg, 0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
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#define REG_SPI1_IMR REG_ACCESS(RoReg, 0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
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#define REG_SPI1_CSR REG_ACCESS(RwReg, 0x4000C030U) /**< \brief (SPI1) Chip Select Register */
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#define REG_SPI1_WPMR REG_ACCESS(RwReg, 0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
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#define REG_SPI1_WPSR REG_ACCESS(RoReg, 0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
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#endif /* _SAM3XA_SPI1_INSTANCE_ */
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