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740 lines
43 KiB
C
740 lines
43 KiB
C
/*
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Copyright (c) 2012 Arduino. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef UOTGHS_H_INCLUDED
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#define UOTGHS_H_INCLUDED
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#define MAX_ENDPOINTS 10
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#define EP0 0
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#define EP_SINGLE_64 (0x32UL) // EP0
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#define EP_DOUBLE_64 (0x36UL) // Other endpoints
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// Control Endpoint
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#define EP_TYPE_CONTROL (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_CTRL | \
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UOTGHS_DEVEPTCFG_EPBK_1_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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// CDC Endpoints
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#define EP_TYPE_BULK_IN (UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_BLK | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_BULK_OUT (UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_BLK | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_INTERRUPT_IN (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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// HID Endpoints
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#define EP_TYPE_INTERRUPT_IN_HID (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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// Various definitions
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#define EP_TYPE_INTERRUPT_OUT (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPBK_1_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_ISOCHRONOUS_IN (UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_ISO | \
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UOTGHS_DEVEPTCFG_EPBK_3_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_ISOCHRONOUS_OUT (UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_ISO | \
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UOTGHS_DEVEPTCFG_EPBK_3_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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//! \ingroup usb_device_group
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//! \defgroup udd_group USB Device Driver (UDD)
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//! UOTGHS low-level driver for USB device mode
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//!
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//! @{
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#ifndef UOTGHS_DEVEPTCFG_EPDIR_Pos
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// Bit pos is not defined in SAM header file but we need it.
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# define UOTGHS_DEVEPTCFG_EPDIR_Pos 8
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#endif
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//! @name UOTGHS Device IP properties
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//! These macros give access to IP properties
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//! @{
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//! Get maximal number of endpoints
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#define udd_get_endpoint_max_nbr() (9)
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#define UDD_MAX_PEP_NB (udd_get_endpoint_max_nbr() + 1)
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//! Get maximal number of banks of endpoints
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#define udd_get_endpoint_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2))
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//! Get maximal size of endpoint (3X, 1024/64)
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#define udd_get_endpoint_size_max(ep) (((ep) == 0) ? 64 : 1024)
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//! Get DMA support of endpoints
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#define Is_udd_endpoint_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 6)) ? true : false)
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//! Get High Band Width support of endpoints
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#define Is_udd_endpoint_high_bw_supported(ep) (((ep) >= 2) ? true : false)
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//! @}
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//! @name UOTGHS Device speeds management
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//! @{
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//! Enable/disable device low-speed mode
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#define udd_low_speed_enable() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
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#define udd_low_speed_disable() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
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//! Test if device low-speed mode is forced
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#define Is_udd_low_speed_enable() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
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//! Enable high speed mode
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#define udd_high_speed_enable() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 0))
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//! Disable high speed mode
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#define udd_high_speed_disable() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 3))
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//! Test if controller is in full speed mode
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#define Is_udd_full_speed_mode() (Rd_bitfield(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk) == UOTGHS_SR_SPEED_FULL_SPEED)
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//! @}
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//! @name UOTGHS Device HS test mode management
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//! @{
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#ifdef UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED
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//! Enable high speed test mode
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# define udd_enable_hs_test_mode() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 2))
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# define udd_enable_hs_test_mode_j() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTJ))
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# define udd_enable_hs_test_mode_k() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTK))
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# define udd_enable_hs_test_mode_packet() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTPCKT))
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#endif
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//! @}
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//! @name UOTGHS Device vbus management
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//! @{
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#define udd_enable_vbus_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
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#define udd_disable_vbus_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
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#define Is_udd_vbus_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
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#define Is_udd_vbus_high() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS))
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#define Is_udd_vbus_low() (!Is_udd_vbus_high())
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#define udd_ack_vbus_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC)
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#define udd_raise_vbus_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS)
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#define Is_udd_vbus_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI))
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//! @}
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//! @name UOTGHS device attach control
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//! These macros manage the UOTGHS Device attach.
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//! @{
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//! Detaches from USB bus
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#define udd_detach_device() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
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//! Attaches to USB bus
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#define udd_attach_device() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
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//! Test if the device is detached
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#define Is_udd_detached() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
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//! @}
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//! @name UOTGHS device bus events control
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//! These macros manage the UOTGHS Device bus events.
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//! @{
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//! Initiates a remote wake-up event
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//! @{
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#define udd_initiate_remote_wake_up() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP))
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#define Is_udd_pending_remote_wake_up() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP))
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//! @}
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//! Manage upstream resume event (=remote wakeup)
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//! The USB driver sends a resume signal called "Upstream Resume"
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//! @{
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#define udd_enable_remote_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_UPRSMES)
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#define udd_disable_remote_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_UPRSMEC)
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#define Is_udd_remote_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_UPRSME))
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#define udd_ack_remote_wake_up_start() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_UPRSMC)
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#define udd_raise_remote_wake_up_start() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_UPRSMS)
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#define Is_udd_remote_wake_up_start() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_UPRSM))
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//! @}
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//! Manage downstream resume event (=remote wakeup from host)
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//! The USB controller detects a valid "End of Resume" signal initiated by the host
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//! @{
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#define udd_enable_resume_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSMES)
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#define udd_disable_resume_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSMEC)
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#define Is_udd_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSME))
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#define udd_ack_resume() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSMC)
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#define udd_raise_resume() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSMS)
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#define Is_udd_resume() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORSM))
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//! @}
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//! Manage wake-up event (=usb line activity)
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//! The USB controller is reactivated by a filtered non-idle signal from the lines
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//! @{
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#define udd_enable_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES)
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#define udd_disable_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_WAKEUPEC)
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#define Is_udd_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_WAKEUPE))
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#define udd_ack_wake_up() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_WAKEUPC)
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#define udd_raise_wake_up() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_WAKEUPS)
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#define Is_udd_wake_up() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_WAKEUP))
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//! @}
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//! Manage reset event
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//! Set when a USB "End of Reset" has been detected
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//! @{
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#define udd_enable_reset_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSTES)
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#define udd_disable_reset_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSTEC)
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#define Is_udd_reset_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSTE))
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#define udd_ack_reset() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSTC)
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#define udd_raise_reset() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSTS)
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#define Is_udd_reset() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORST))
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//! @}
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//! Manage start of frame event
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//! @{
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#define udd_enable_sof_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SOFES)
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#define udd_disable_sof_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SOFEC)
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#define Is_udd_sof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SOFE))
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#define udd_ack_sof() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SOFC)
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#define udd_raise_sof() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SOFS)
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#define Is_udd_sof() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SOF))
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#define udd_frame_number() (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNUM_Msk))
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#define Is_udd_frame_number_crc_error() (Tst_bits(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNCERR))
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//! @}
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//! Manage Micro start of frame event (High Speed Only)
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//! @{
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#define udd_enable_msof_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_MSOFES)
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#define udd_disable_msof_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_MSOFEC)
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#define Is_udd_msof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_MSOFE))
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#define udd_ack_msof() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVIMR_MSOFE)
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#define udd_raise_msof() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_MSOFS)
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#define Is_udd_msof() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_MSOF))
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#define udd_micro_frame_number() \
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(Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, (UOTGHS_DEVFNUM_FNUM_Msk|UOTGHS_DEVFNUM_MFNUM_Msk)))
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//! @}
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//! Manage suspend event
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//! @{
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#define udd_enable_suspend_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SUSPES)
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#define udd_disable_suspend_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SUSPEC)
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#define Is_udd_suspend_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SUSPE))
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#define udd_ack_suspend() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SUSPC)
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#define udd_raise_suspend() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SUSPS)
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#define Is_udd_suspend() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SUSP))
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//! @}
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//! @}
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//! @name UOTGHS device address control
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//! These macros manage the UOTGHS Device address.
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//! @{
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//! enables USB device address
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#define udd_enable_address() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
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//! disables USB device address
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#define udd_disable_address() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
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#define Is_udd_address_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
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//! configures the USB device address
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#define udd_configure_address(addr) (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk, addr))
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//! gets the currently configured USB device address
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#define udd_get_configured_address() (Rd_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk))
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//! @}
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//! @name UOTGHS Device endpoint drivers
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//! These macros manage the common features of the endpoints.
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//! @{
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//! Generic macro for UOTGHS registers that can be arrayed
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//! @{
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#define UOTGHS_ARRAY(reg,index) ((&(UOTGHS->reg))[(index)])
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//! @}
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//! @name UOTGHS Device endpoint configuration
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//! @{
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//! enables the selected endpoint
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#define udd_enable_endpoint(ep) (Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep)))
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//! disables the selected endpoint
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#define udd_disable_endpoint(ep) (Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep)))
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//! tests if the selected endpoint is enabled
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#define Is_udd_endpoint_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep)))
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//! resets the selected endpoint
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#define udd_reset_endpoint(ep) \
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do { \
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Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \
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Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \
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} while (0)
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//! Tests if the selected endpoint is being reset
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#define Is_udd_resetting_endpoint(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)))
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//! Configures the selected endpoint type
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#define udd_configure_endpoint_type(ep, type) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk, type))
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//! Gets the configured selected endpoint type
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#define udd_get_endpoint_type(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk))
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//! Enables the bank autoswitch for the selected endpoint
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#define udd_enable_endpoint_bank_autoswitch(ep) (Set_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW))
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//! Disables the bank autoswitch for the selected endpoint
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#define udd_disable_endpoint_bank_autoswitch(ep) (Clr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW))
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#define Is_udd_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW))
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//! Configures the selected endpoint direction
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#define udd_configure_endpoint_direction(ep, dir) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR, dir))
|
|
//! Gets the configured selected endpoint direction
|
|
#define udd_get_endpoint_direction(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR))
|
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#define Is_udd_endpoint_in(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR))
|
|
//! Bounds given integer size to allowed range and rounds it up to the nearest
|
|
//! available greater size, then applies register format of UOTGHS controller
|
|
//! for endpoint size bit-field.
|
|
#define udd_format_endpoint_size(size) (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
|
|
//! Configures the selected endpoint size
|
|
#define udd_configure_endpoint_size(ep, size) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk, udd_format_endpoint_size(size)))
|
|
//! Gets the configured selected endpoint size
|
|
#define udd_get_endpoint_size(ep) (8 << Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk))
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|
//! Configures the selected endpoint number of banks
|
|
#define udd_configure_endpoint_bank(ep, bank) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPBK_Msk, bank))
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|
//! Gets the configured selected endpoint number of banks
|
|
#define udd_get_endpoint_bank(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPBK_Msk)+1)
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|
//! Allocates the configuration selected endpoint in DPRAM memory
|
|
#define udd_allocate_memory(ep) (Set_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC))
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|
//! un-allocates the configuration selected endpoint in DPRAM memory
|
|
#define udd_unallocate_memory(ep) (Clr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC))
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#define Is_udd_memory_allocated(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC))
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|
|
|
//! Configures selected endpoint in one step
|
|
#define udd_configure_endpoint(ep, type, dir, size, bank) (\
|
|
Wr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk |\
|
|
UOTGHS_DEVEPTCFG_EPDIR |\
|
|
UOTGHS_DEVEPTCFG_EPSIZE_Msk |\
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|
UOTGHS_DEVEPTCFG_EPBK_Msk , \
|
|
(((uint32_t)(type) << UOTGHS_DEVEPTCFG_EPTYPE_Pos) & UOTGHS_DEVEPTCFG_EPTYPE_Msk) |\
|
|
(((uint32_t)(dir ) << UOTGHS_DEVEPTCFG_EPDIR_Pos ) & UOTGHS_DEVEPTCFG_EPDIR) |\
|
|
( (uint32_t)udd_format_endpoint_size(size) << UOTGHS_DEVEPTCFG_EPSIZE_Pos) |\
|
|
(((uint32_t)(bank) << UOTGHS_DEVEPTCFG_EPBK_Pos) & UOTGHS_DEVEPTCFG_EPBK_Msk))\
|
|
)
|
|
//! Tests if current endpoint is configured
|
|
#define Is_udd_endpoint_configured(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CFGOK))
|
|
//! Returns the control direction
|
|
#define udd_control_direction() (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], EP_CONTROL), UOTGHS_DEVEPTISR_CTRLDIR))
|
|
|
|
//! Resets the data toggle sequence
|
|
#define udd_reset_data_toggle(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RSTDTS)
|
|
//! Tests if the data toggle sequence is being reset
|
|
#define Is_udd_data_toggle_reset(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RSTDT))
|
|
//! Returns data toggle
|
|
#define udd_data_toggle(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_DTSEQ_Msk))
|
|
//! @}
|
|
|
|
|
|
//! @name UOTGHS Device control endpoint
|
|
//! These macros control the endpoints.
|
|
//! @{
|
|
|
|
//! @name UOTGHS Device control endpoint interrupts
|
|
//! These macros control the endpoints interrupts.
|
|
//! @{
|
|
//! Enables the selected endpoint interrupt
|
|
#define udd_enable_endpoint_interrupt(ep) (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_PEP_0 << (ep))
|
|
//! Disables the selected endpoint interrupt
|
|
#define udd_disable_endpoint_interrupt(ep) (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_PEP_0 << (ep))
|
|
//! Tests if the selected endpoint interrupt is enabled
|
|
#define Is_udd_endpoint_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_PEP_0 << (ep)))
|
|
//! Tests if an interrupt is triggered by the selected endpoint
|
|
#define Is_udd_endpoint_interrupt(ep) (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_PEP_0 << (ep)))
|
|
//! Returns the lowest endpoint number generating an endpoint interrupt or MAX_PEP_NB if none
|
|
#define udd_get_interrupt_endpoint_number() (ctz(((UOTGHS->UOTGHS_DEVISR >> UOTGHS_DEVISR_PEP_Pos) & \
|
|
(UOTGHS->UOTGHS_DEVIMR >> UOTGHS_DEVIMR_PEP_Pos)) | \
|
|
(1 << MAX_PEP_NB)))
|
|
#define UOTGHS_DEVISR_PEP_Pos 12
|
|
#define UOTGHS_DEVIMR_PEP_Pos 12
|
|
//! @}
|
|
|
|
//! @name UOTGHS Device control endpoint errors
|
|
//! These macros control the endpoint errors.
|
|
//! @{
|
|
//! Enables the STALL handshake
|
|
#define udd_enable_stall_handshake(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_STALLRQS)
|
|
//! Disables the STALL handshake
|
|
#define udd_disable_stall_handshake(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_STALLRQC)
|
|
//! Tests if STALL handshake request is running
|
|
#define Is_udd_endpoint_stall_requested(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_STALLRQ))
|
|
//! Tests if STALL sent
|
|
#define Is_udd_stall(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_STALLEDI))
|
|
//! ACKs STALL sent
|
|
#define udd_ack_stall(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_STALLEDIC)
|
|
//! Raises STALL sent
|
|
#define udd_raise_stall(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_STALLEDIS)
|
|
//! Enables STALL sent interrupt
|
|
#define udd_enable_stall_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_STALLEDES)
|
|
//! Disables STALL sent interrupt
|
|
#define udd_disable_stall_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_STALLEDEC)
|
|
//! Tests if STALL sent interrupt is enabled
|
|
#define Is_udd_stall_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_STALLEDE))
|
|
|
|
//! Tests if NAK OUT received
|
|
#define Is_udd_nak_out(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NAKOUTI))
|
|
//! ACKs NAK OUT received
|
|
#define udd_ack_nak_out(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_NAKOUTIC)
|
|
//! Raises NAK OUT received
|
|
#define udd_raise_nak_out(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NAKOUTIS)
|
|
//! Enables NAK OUT interrupt
|
|
#define udd_enable_nak_out_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NAKOUTES)
|
|
//! Disables NAK OUT interrupt
|
|
#define udd_disable_nak_out_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NAKOUTEC)
|
|
//! Tests if NAK OUT interrupt is enabled
|
|
#define Is_udd_nak_out_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NAKOUTE))
|
|
|
|
//! Tests if NAK IN received
|
|
#define Is_udd_nak_in(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NAKINI))
|
|
//! ACKs NAK IN received
|
|
#define udd_ack_nak_in(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_NAKINIC)
|
|
//! Raises NAK IN received
|
|
#define udd_raise_nak_in(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NAKINIS)
|
|
//! Enables NAK IN interrupt
|
|
#define udd_enable_nak_in_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NAKINES)
|
|
//! Disables NAK IN interrupt
|
|
#define udd_disable_nak_in_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NAKINEC)
|
|
//! Tests if NAK IN interrupt is enabled
|
|
#define Is_udd_nak_in_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NAKINE))
|
|
|
|
//! ACKs endpoint isochronous overflow interrupt
|
|
#define udd_ack_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_OVERFIC)
|
|
//! Raises endpoint isochronous overflow interrupt
|
|
#define udd_raise_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_OVERFIS)
|
|
//! Tests if an overflow occurs
|
|
#define Is_udd_overflow(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_OVERFI))
|
|
//! Enables overflow interrupt
|
|
#define udd_enable_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_OVERFES)
|
|
//! Disables overflow interrupt
|
|
#define udd_disable_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_OVERFEC)
|
|
//! Tests if overflow interrupt is enabled
|
|
#define Is_udd_overflow_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_OVERFE))
|
|
|
|
//! ACKs endpoint isochronous underflow interrupt
|
|
#define udd_ack_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_UNDERFIC)
|
|
//! Raises endpoint isochronous underflow interrupt
|
|
#define udd_raise_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_UNDERFIS)
|
|
//! Tests if an underflow occurs
|
|
#define Is_udd_underflow(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_UNDERFI))
|
|
//! Enables underflow interrupt
|
|
#define udd_enable_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_UNDERFES)
|
|
//! Disables underflow interrupt
|
|
#define udd_disable_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_UNDERFEC)
|
|
//! Tests if underflow interrupt is enabled
|
|
#define Is_udd_underflow_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_UNDERFE))
|
|
|
|
//! Tests if CRC ERROR ISO OUT detected
|
|
#define Is_udd_crc_error(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CRCERRI))
|
|
//! ACKs CRC ERROR ISO OUT detected
|
|
#define udd_ack_crc_error(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_CRCERRIC)
|
|
//! Raises CRC ERROR ISO OUT detected
|
|
#define udd_raise_crc_error(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_CRCERRIS)
|
|
//! Enables CRC ERROR ISO OUT detected interrupt
|
|
#define udd_enable_crc_error_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_CRCERRES)
|
|
//! Disables CRC ERROR ISO OUT detected interrupt
|
|
#define udd_disable_crc_error_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_CRCERREC)
|
|
//! Tests if CRC ERROR ISO OUT detected interrupt is enabled
|
|
#define Is_udd_crc_error_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_CRCERRE))
|
|
//! @}
|
|
|
|
//! @name UOTGHS Device control endpoint transfer
|
|
//! These macros control the endpoint transfer.
|
|
//! @{
|
|
|
|
//! Tests if endpoint read allowed
|
|
#define Is_udd_read_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RWALL))
|
|
//! Tests if endpoint write allowed
|
|
#define Is_udd_write_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RWALL))
|
|
|
|
//! Returns the byte count
|
|
#define udd_byte_count(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_BYCT_Msk))
|
|
//! Clears FIFOCON bit
|
|
#define udd_ack_fifocon(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_FIFOCONC)
|
|
//! Tests if FIFOCON bit set
|
|
#define Is_udd_fifocon(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_FIFOCON))
|
|
|
|
//! Returns the number of busy banks
|
|
#define udd_nb_busy_bank(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NBUSYBK_Msk))
|
|
//! Returns the number of the current bank
|
|
#define udd_current_bank(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CURRBK_Msk))
|
|
//! Kills last bank
|
|
#define udd_kill_last_in_bank(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_KILLBKS)
|
|
#define Is_udd_kill_last(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_KILLBK))
|
|
//! Tests if last bank killed
|
|
#define Is_udd_last_in_bank_killed(ep) (!Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_KILLBK))
|
|
//! Forces all banks full (OUT) or free (IN) interrupt
|
|
#define udd_force_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NBUSYBKS)
|
|
//! Unforces all banks full (OUT) or free (IN) interrupt
|
|
#define udd_unforce_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NBUSYBKS)
|
|
//! Enables all banks full (OUT) or free (IN) interrupt
|
|
#define udd_enable_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NBUSYBKES)
|
|
//! Disables all banks full (OUT) or free (IN) interrupt
|
|
#define udd_disable_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NBUSYBKEC)
|
|
//! Tests if all banks full (OUT) or free (IN) interrupt enabled
|
|
#define Is_udd_bank_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NBUSYBKE))
|
|
|
|
//! Tests if SHORT PACKET received
|
|
#define Is_udd_short_packet(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_SHORTPACKET))
|
|
//! ACKs SHORT PACKET received
|
|
#define udd_ack_short_packet(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_SHORTPACKETC)
|
|
//! Raises SHORT PACKET received
|
|
#define udd_raise_short_packet(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_SHORTPACKETS)
|
|
//! Enables SHORT PACKET received interrupt
|
|
#define udd_enable_short_packet_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_SHORTPACKETES)
|
|
//! Disables SHORT PACKET received interrupt
|
|
#define udd_disable_short_packet_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_SHORTPACKETEC)
|
|
//! Tests if SHORT PACKET received interrupt is enabled
|
|
#define Is_udd_short_packet_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_SHORTPACKETE))
|
|
|
|
//! Tests if SETUP received
|
|
#define Is_udd_setup_received(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RXSTPI))
|
|
//! ACKs SETUP received
|
|
#define udd_ack_setup_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_RXSTPIC)
|
|
//! Raises SETUP received
|
|
#define udd_raise_setup_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_RXSTPIS)
|
|
//! Enables SETUP received interrupt
|
|
#define udd_enable_setup_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RXSTPES)
|
|
//! Disables SETUP received interrupt
|
|
#define udd_disable_setup_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_RXSTPEC)
|
|
//! Tests if SETUP received interrupt is enabled
|
|
#define Is_udd_setup_received_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RXSTPE))
|
|
|
|
//! Tests if OUT received
|
|
#define Is_udd_out_received(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RXOUTI))
|
|
//! ACKs OUT received
|
|
#define udd_ack_out_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_RXOUTIC)
|
|
//! Raises OUT received
|
|
#define udd_raise_out_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_RXOUTIS)
|
|
//! Enables OUT received interrupt
|
|
#define udd_enable_out_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RXOUTES)
|
|
//! Disables OUT received interrupt
|
|
#define udd_disable_out_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_RXOUTEC)
|
|
//! Tests if OUT received interrupt is enabled
|
|
#define Is_udd_out_received_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RXOUTE))
|
|
|
|
//! Tests if IN sending
|
|
#define Is_udd_in_send(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_TXINI))
|
|
//! ACKs IN sending
|
|
#define udd_ack_in_send(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_TXINIC)
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//! Raises IN sending
|
|
#define udd_raise_in_send(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_TXINIS)
|
|
//! Enables IN sending interrupt
|
|
#define udd_enable_in_send_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_TXINES)
|
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//! Disables IN sending interrupt
|
|
#define udd_disable_in_send_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_TXINEC)
|
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//! Tests if IN sending interrupt is enabled
|
|
#define Is_udd_in_send_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_TXINE))
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|
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//! 8-bit access to FIFO data register of selected endpoint.
|
|
//! @param ep Endpoint of which to access FIFO data register
|
|
//! @return Volatile 8-bit data pointer to FIFO data register
|
|
//! @warning It is up to the user of this macro to make sure that all accesses
|
|
//! are aligned with their natural boundaries
|
|
//! @warning It is up to the user of this macro to make sure that used HSB
|
|
//! addresses are identical to the DPRAM internal pointer modulo 32 bits.
|
|
#define udd_get_endpoint_fifo_access8(ep) \
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(((volatile uint8_t (*)[0x8000])UOTGHS_RAM_ADDR)[(ep)])
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//! @}
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/*********************************************************************************************************************/
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//! @name UOTGHS IP properties
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//! These macros give access to IP properties (not defined in 3X)
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//! @{
|
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//! Get IP name part 1 or 2
|
|
#define otg_get_ip_name()
|
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#define otg_data_memory_barrier()
|
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//! Get IP version
|
|
#define otg_get_ip_version()
|
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//! Get DPRAM size (FIFO maximal size) in bytes
|
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#define otg_get_dpram_size()
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//! Get size of USBB PB address space
|
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#define otg_get_ip_paddress_size()
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//! @}
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//! @name UOTGHS OTG ID pin management
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//! The ID pin come from the USB OTG connector (A and B receptable) and
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//! allows to select the USB mode host or device.
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//! The USBB hardware can manage it automaticaly. This feature is optional.
|
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//! When otg_ID_PIN equals true in conf_usb_host.h, the USB_ID must be defined in board.h.
|
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//!
|
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//! @{
|
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//! PIO, PIO ID and MASK for USB_ID according to configuration from OTG_ID
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#define OTG_ID_PIN USB_ID_GPIO
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#define OTG_ID_FUNCTION USB_ID_FLAGS
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//! Input USB_ID from its pin
|
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#define otg_input_id_pin() do { \
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pio_configure_pin(OTG_ID_PIN, OTG_ID_FUNCTION); \
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} while (0)
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|
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//! Enable external OTG_ID pin (listened to by USB)
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|
#define otg_enable_id_pin() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
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//! Disable external OTG_ID pin (ignored by USB)
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#define otg_disable_id_pin() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
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//! Test if external OTG_ID pin enabled (listened to by USB)
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|
#define Is_otg_id_pin_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
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//! Disable external OTG_ID pin and force device mode
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#define otg_force_device_mode() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), otg_disable_id_pin())
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//! Test if device mode is forced
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#define Is_otg_device_mode_forced() (!Is_otg_id_pin_enabled() && Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD))
|
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//! Disable external OTG_ID pin and force host mode
|
|
#define otg_force_host_mode() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), otg_disable_id_pin())
|
|
//! Test if host mode is forced
|
|
#define Is_otg_host_mode_forced() (!Is_otg_id_pin_enabled() && !Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD))
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|
|
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//! @name UOTGHS OTG ID pin interrupt management
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|
//! These macros manage the ID pin interrupt
|
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//! @{
|
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#define otg_enable_id_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
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#define otg_disable_id_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
|
|
#define Is_otg_id_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
|
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#define Is_otg_id_device() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ID))
|
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#define Is_otg_id_host() (!Is_otg_id_device())
|
|
#define otg_ack_id_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_IDTIC)
|
|
#define otg_raise_id_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_IDTIS)
|
|
#define Is_otg_id_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_IDTI))
|
|
//! @}
|
|
|
|
//! @name USBB OTG Vbus management
|
|
//! @{
|
|
#define otg_enable_vbus_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
|
|
#define otg_disable_vbus_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
|
|
#define Is_otg_vbus_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
|
|
#define Is_otg_vbus_high() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS))
|
|
#define Is_otg_vbus_low() (!Is_otg_vbus_high())
|
|
#define otg_ack_vbus_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC)
|
|
#define otg_raise_vbus_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS)
|
|
#define Is_otg_vbus_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI))
|
|
//! @}
|
|
|
|
//! @name UOTGHS OTG main management
|
|
//! These macros allows to enable/disable pad and UOTGHS hardware
|
|
//! @{
|
|
//! Enable USB macro
|
|
#define otg_enable() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
|
|
//! Disable USB macro
|
|
#define otg_disable() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
|
|
#define Is_otg_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
|
|
|
|
//! Enable OTG pad
|
|
#define otg_enable_pad() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
|
|
//! Disable OTG pad
|
|
#define otg_disable_pad() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
|
|
#define Is_otg_pad_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
|
|
|
|
//! Check Clock Usable
|
|
//! For parts with HS feature, this one corresponding at UTMI clock
|
|
#define Is_otg_clock_usable() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_CLKUSABLE))
|
|
|
|
//! Stop (freeze) internal USB clock
|
|
#define otg_freeze_clock() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
|
|
#define otg_unfreeze_clock() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
|
|
#define Is_otg_clock_frozen() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
|
|
|
|
//! Configure time-out of specified OTG timer
|
|
#define otg_configure_timeout(timer, timeout) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
|
|
Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer),\
|
|
Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk, timeout),\
|
|
Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK))
|
|
//! Get configured time-out of specified OTG timer
|
|
#define otg_get_timeout(timer) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
|
|
Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer),\
|
|
Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
|
|
Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk))
|
|
|
|
|
|
//! Get the dual-role device state of the internal USB finite state machine of the UOTGHS controller
|
|
#define otg_get_fsm_drd_state() (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk))
|
|
//! @}
|
|
|
|
//! @name UOTGHS OTG hardware protocol
|
|
//! These macros manages the hardware OTG protocol
|
|
//! @{
|
|
//! Initiates a Host Negociation Protocol
|
|
#define otg_device_initiate_hnp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
|
|
//! Accepts a Host Negociation Protocol
|
|
#define otg_host_accept_hnp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
|
|
//! Rejects a Host Negociation Protocol
|
|
#define otg_host_reject_hnp() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
|
|
//! initiates a Session Request Protocol
|
|
#define otg_device_initiate_srp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ))
|
|
//! Selects VBus as SRP method
|
|
#define otg_select_vbus_srp_method() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
|
|
#define Is_otg_vbus_srp_method_selected() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
|
|
//! Selects data line as SRP method
|
|
#define otg_select_data_srp_method() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
|
|
#define Is_otg_data_srp_method_selected() (!Is_otg_vbus_srp_method_selected())
|
|
//! Tests if a HNP occurs
|
|
#define Is_otg_hnp() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
|
|
//! Tests if a SRP from device occurs
|
|
#define Is_otg_device_srp() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ))
|
|
|
|
//! Enables HNP error interrupt
|
|
#define otg_enable_hnp_error_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
|
|
//! Disables HNP error interrupt
|
|
#define otg_disable_hnp_error_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
|
|
#define Is_otg_hnp_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
|
|
//! ACKs HNP error interrupt
|
|
#define otg_ack_hnp_error_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_HNPERRIC)
|
|
//! Raises HNP error interrupt
|
|
#define otg_raise_hnp_error_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_HNPERRIS)
|
|
//! Tests if a HNP error occurs
|
|
#define Is_otg_hnp_error_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_HNPERRI))
|
|
|
|
//! Enables role exchange interrupt
|
|
#define otg_enable_role_exchange_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
|
|
//! Disables role exchange interrupt
|
|
#define otg_disable_role_exchange_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
|
|
#define Is_otg_role_exchange_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
|
|
//! ACKs role exchange interrupt
|
|
#define otg_ack_role_exchange_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_ROLEEXIC)
|
|
//! Raises role exchange interrupt
|
|
#define otg_raise_role_exchange_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_ROLEEXIS)
|
|
//! Tests if a role exchange occurs
|
|
#define Is_otg_role_exchange_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ROLEEXI))
|
|
|
|
//! Eenables SRP interrupt
|
|
#define otg_enable_srp_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
|
|
//! Disables SRP interrupt
|
|
#define otg_disable_srp_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
|
|
#define Is_otg_srp_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
|
|
//! ACKs SRP interrupt
|
|
#define otg_ack_srp_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_SRPIC)
|
|
//! Raises SRP interrupt
|
|
#define otg_raise_srp_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_SRPIS)
|
|
//! Tests if a SRP occurs
|
|
#define Is_otg_srp_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_SRPI))
|
|
//! @}
|
|
|
|
//! @}
|
|
|
|
|
|
#endif /* UOTGHS_H_INCLUDED */
|