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68 lines
5.6 KiB
C
68 lines
5.6 KiB
C
/* $asf_license$ */
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#ifndef _SAM3S8_USART2_INSTANCE_
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#define _SAM3S8_USART2_INSTANCE_
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/* ========== Register definition for USART2 peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */
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#define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */
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#define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
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#define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
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#define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
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#define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */
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#define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
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#define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
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#define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
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#define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
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#define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
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#define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
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#define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */
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#define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
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#define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
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#define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
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#define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
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#define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */
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#define REG_USART2_RPR (0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
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#define REG_USART2_RCR (0x4002C104U) /**< \brief (USART2) Receive Counter Register */
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#define REG_USART2_TPR (0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
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#define REG_USART2_TCR (0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
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#define REG_USART2_RNPR (0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
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#define REG_USART2_RNCR (0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
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#define REG_USART2_TNPR (0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
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#define REG_USART2_TNCR (0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
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#define REG_USART2_PTCR (0x4002C120U) /**< \brief (USART2) Transfer Control Register */
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#define REG_USART2_PTSR (0x4002C124U) /**< \brief (USART2) Transfer Status Register */
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#else
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#define REG_USART2_CR (*(WoReg*)0x4002C000U) /**< \brief (USART2) Control Register */
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#define REG_USART2_MR (*(RwReg*)0x4002C004U) /**< \brief (USART2) Mode Register */
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#define REG_USART2_IER (*(WoReg*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
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#define REG_USART2_IDR (*(WoReg*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
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#define REG_USART2_IMR (*(RoReg*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
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#define REG_USART2_CSR (*(RoReg*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
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#define REG_USART2_RHR (*(RoReg*)0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
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#define REG_USART2_THR (*(WoReg*)0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
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#define REG_USART2_BRGR (*(RwReg*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
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#define REG_USART2_RTOR (*(RwReg*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
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#define REG_USART2_TTGR (*(RwReg*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
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#define REG_USART2_FIDI (*(RwReg*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
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#define REG_USART2_NER (*(RoReg*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */
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#define REG_USART2_IF (*(RwReg*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
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#define REG_USART2_MAN (*(RwReg*)0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
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#define REG_USART2_WPMR (*(RwReg*)0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
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#define REG_USART2_WPSR (*(RoReg*)0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
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#define REG_USART2_VERSION (*(RoReg*)0x4002C0FCU) /**< \brief (USART2) Version Register */
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#define REG_USART2_RPR (*(RwReg*)0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
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#define REG_USART2_RCR (*(RwReg*)0x4002C104U) /**< \brief (USART2) Receive Counter Register */
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#define REG_USART2_TPR (*(RwReg*)0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
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#define REG_USART2_TCR (*(RwReg*)0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
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#define REG_USART2_RNPR (*(RwReg*)0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
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#define REG_USART2_RNCR (*(RwReg*)0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
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#define REG_USART2_TNPR (*(RwReg*)0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
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#define REG_USART2_TNCR (*(RwReg*)0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
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#define REG_USART2_PTCR (*(WoReg*)0x4002C120U) /**< \brief (USART2) Transfer Control Register */
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#define REG_USART2_PTSR (*(RoReg*)0x4002C124U) /**< \brief (USART2) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3S8_USART2_INSTANCE_ */
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