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68 lines
5.8 KiB
C
68 lines
5.8 KiB
C
/* $asf_license$ */
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#ifndef _SAM3N_PWM_INSTANCE_
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#define _SAM3N_PWM_INSTANCE_
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/* ========== Register definition for PWM peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_PWM_MR (0x40020000U) /**< \brief (PWM) PWM Mode Register */
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#define REG_PWM_ENA (0x40020004U) /**< \brief (PWM) PWM Enable Register */
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#define REG_PWM_DIS (0x40020008U) /**< \brief (PWM) PWM Disable Register */
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#define REG_PWM_SR (0x4002000CU) /**< \brief (PWM) PWM Status Register */
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#define REG_PWM_IER (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
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#define REG_PWM_IDR (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
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#define REG_PWM_IMR (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
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#define REG_PWM_ISR (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
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#define REG_PWM_CMR0 (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
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#define REG_PWM_CDTY0 (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
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#define REG_PWM_CPRD0 (0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
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#define REG_PWM_CCNT0 (0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
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#define REG_PWM_CUPD0 (0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
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#define REG_PWM_CMR1 (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
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#define REG_PWM_CDTY1 (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
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#define REG_PWM_CPRD1 (0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
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#define REG_PWM_CCNT1 (0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
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#define REG_PWM_CUPD1 (0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
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#define REG_PWM_CMR2 (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
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#define REG_PWM_CDTY2 (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
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#define REG_PWM_CPRD2 (0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
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#define REG_PWM_CCNT2 (0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
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#define REG_PWM_CUPD2 (0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
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#define REG_PWM_CMR3 (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
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#define REG_PWM_CDTY3 (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
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#define REG_PWM_CPRD3 (0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
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#define REG_PWM_CCNT3 (0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
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#define REG_PWM_CUPD3 (0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
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#else
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#define REG_PWM_MR (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Mode Register */
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#define REG_PWM_ENA (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
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#define REG_PWM_DIS (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
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#define REG_PWM_SR (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
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#define REG_PWM_IER (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
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#define REG_PWM_IDR (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
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#define REG_PWM_IMR (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
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#define REG_PWM_ISR (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
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#define REG_PWM_CMR0 (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
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#define REG_PWM_CDTY0 (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
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#define REG_PWM_CPRD0 (*(RwReg*)0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
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#define REG_PWM_CCNT0 (*(RoReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
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#define REG_PWM_CUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
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#define REG_PWM_CMR1 (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
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#define REG_PWM_CDTY1 (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
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#define REG_PWM_CPRD1 (*(RwReg*)0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
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#define REG_PWM_CCNT1 (*(RoReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
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#define REG_PWM_CUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
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#define REG_PWM_CMR2 (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
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#define REG_PWM_CDTY2 (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
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#define REG_PWM_CPRD2 (*(RwReg*)0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
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#define REG_PWM_CCNT2 (*(RoReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
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#define REG_PWM_CUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
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#define REG_PWM_CMR3 (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
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#define REG_PWM_CDTY3 (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
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#define REG_PWM_CPRD3 (*(RwReg*)0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
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#define REG_PWM_CCNT3 (*(RoReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
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#define REG_PWM_CUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3N_PWM_INSTANCE_ */
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