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421 lines
22 KiB
C
421 lines
22 KiB
C
/* $asf_license$ */
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#ifndef _SAM3X8G_
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#define _SAM3X8G_
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/** \addtogroup SAM3X8G_definitions SAM3X8G definitions
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This file defines all structures and symbols for SAM3X8G:
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- registers and bitfields
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- peripheral base address
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- peripheral ID
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- PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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#endif
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/* ************************************************************************** */
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/* CMSIS DEFINITIONS FOR SAM3X8G */
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/* ************************************************************************** */
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/** \addtogroup SAM3X8G_cmsis CMSIS Definitions */
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/*@{*/
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/**< Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ******************************/
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
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/****** SAM3X8G specific Interrupt Numbers *********************************/
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SUPC_IRQn = 0, /**< 0 SAM3X8G Supply Controller (SUPC) */
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RSTC_IRQn = 1, /**< 1 SAM3X8G Reset Controller (RSTC) */
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RTC_IRQn = 2, /**< 2 SAM3X8G Real Time Clock (RTC) */
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RTT_IRQn = 3, /**< 3 SAM3X8G Real Time Timer (RTT) */
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WDT_IRQn = 4, /**< 4 SAM3X8G Watchdog Timer (WDT) */
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PMC_IRQn = 5, /**< 5 SAM3X8G Power Management Controller (PMC) */
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EFC0_IRQn = 6, /**< 6 SAM3X8G Enhanced Flash Controller 0 (EFC0) */
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EFC1_IRQn = 7, /**< 7 SAM3X8G Enhanced Flash Controller 1 (EFC1) */
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UART_IRQn = 8, /**< 8 SAM3X8G Universal Asynchronous Receiver Transceiver (UART) */
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SMC_IRQn = 9, /**< 9 SAM3X8G Static Memory Controller (SMC) */
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SDRAMC_IRQn = 10, /**< 10 SAM3X8G Synchronous Dynamic RAM Controller (SDRAMC) */
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PIOA_IRQn = 11, /**< 11 SAM3X8G Parallel I/O Controller A, (PIOA) */
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PIOB_IRQn = 12, /**< 12 SAM3X8G Parallel I/O Controller B (PIOB) */
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PIOC_IRQn = 13, /**< 13 SAM3X8G Parallel I/O Controller C (PIOC) */
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PIOD_IRQn = 14, /**< 14 SAM3X8G Parallel I/O Controller D (PIOD) */
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PIOE_IRQn = 15, /**< 15 SAM3X8G Parallel I/O Controller E (PIOE) */
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PIOF_IRQn = 16, /**< 16 SAM3X8G Parallel I/O Controller F (PIOF) */
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USART0_IRQn = 17, /**< 17 SAM3X8G USART 0 (USART0) */
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USART1_IRQn = 18, /**< 18 SAM3X8G USART 1 (USART1) */
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USART2_IRQn = 19, /**< 19 SAM3X8G USART 2 (USART2) */
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USART3_IRQn = 20, /**< 20 SAM3X8G USART 3 (USART3) */
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HSMCI_IRQn = 21, /**< 21 SAM3X8G Multimedia Card Interface (HSMCI) */
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TWI0_IRQn = 22, /**< 22 SAM3X8G Two-Wire Interface 0 (TWI0) */
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TWI1_IRQn = 23, /**< 23 SAM3X8G Two-Wire Interface 1 (TWI1) */
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SPI0_IRQn = 24, /**< 24 SAM3X8G Serial Peripheral Interface (SPI0) */
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SPI1_IRQn = 25, /**< 25 SAM3X8G Serial Peripheral Interface (SPI1) */
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SSC_IRQn = 26, /**< 26 SAM3X8G Synchronous Serial Controller (SSC) */
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TC0_IRQn = 27, /**< 27 SAM3X8G Timer Counter 0 (TC0) */
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TC1_IRQn = 28, /**< 28 SAM3X8G Timer Counter 1 (TC1) */
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TC2_IRQn = 29, /**< 29 SAM3X8G Timer Counter 2 (TC2) */
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TC3_IRQn = 30, /**< 30 SAM3X8G Timer Counter 3 (TC3) */
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TC4_IRQn = 31, /**< 31 SAM3X8G Timer Counter 4 (TC4) */
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TC5_IRQn = 32, /**< 32 SAM3X8G Timer Counter 5 (TC5) */
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TC6_IRQn = 33, /**< 33 SAM3X8G Timer Counter 6 (TC6) */
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TC7_IRQn = 34, /**< 34 SAM3X8G Timer Counter 7 (TC7) */
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TC8_IRQn = 35, /**< 35 SAM3X8G Timer Counter 8 (TC8) */
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PWM_IRQn = 36, /**< 36 SAM3X8G Pulse Width Modulation Controller (PWM) */
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ADC_IRQn = 37, /**< 37 SAM3X8G ADC Controller (ADC) */
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DACC_IRQn = 38, /**< 38 SAM3X8G DAC Controller (DACC) */
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DMAC_IRQn = 39, /**< 39 SAM3X8G DMA Controller (DMAC) */
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UOTGHS_IRQn = 40, /**< 40 SAM3X8G USB OTG High Speed (UOTGHS) */
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TRNG_IRQn = 41, /**< 41 SAM3X8G True Random Number Generator (TRNG) */
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EMAC_IRQn = 42, /**< 42 SAM3X8G Ethernet MAC (EMAC) */
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CAN0_IRQn = 43, /**< 43 SAM3X8G CAN Controller 0 (CAN0) */
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CAN1_IRQn = 44 /**< 44 SAM3X8G CAN Controller 1 (CAN1) */
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} IRQn_Type;
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/**
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* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#define __CM3_REV 0x0200 /**< SAM3X8G core revision number ([15:8] revision number, [7:0] patch number) */
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#define __MPU_PRESENT 1 /**< SAM3X8G does provide a MPU */
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#define __NVIC_PRIO_BITS 4 /**< SAM3X8G uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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/*
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* \brief CMSIS includes
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*/
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#include <core_cm3.h>
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8G */
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/* ************************************************************************** */
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/** \addtogroup SAM3X8G_api Peripheral Software API */
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/*@{*/
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#include "component/adc.h"
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#include "component/can.h"
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#include "component/chipid.h"
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#include "component/dacc.h"
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#include "component/dmac.h"
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#include "component/efc.h"
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#include "component/emac.h"
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#include "component/gpbr.h"
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#include "component/hsmci.h"
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#include "component/matrix.h"
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#include "component/pdc.h"
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#include "component/pio.h"
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#include "component/pmc.h"
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#include "component/pwm.h"
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#include "component/rstc.h"
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#include "component/rtc.h"
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#include "component/rtt.h"
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#include "component/sdramc.h"
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#include "component/smc.h"
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#include "component/spi.h"
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#include "component/ssc.h"
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#include "component/supc.h"
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#include "component/tc.h"
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#include "component/trng.h"
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#include "component/twi.h"
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#include "component/uart.h"
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#include "component/uotghs.h"
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#include "component/usart.h"
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#include "component/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/* REGISTER ACCESS DEFINITIONS FOR SAM3X8G */
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/* ************************************************************************** */
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/** \addtogroup SAM3X8G_reg Registers Access Definitions */
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/*@{*/
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#include "instance/hsmci.h"
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#include "instance/ssc.h"
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#include "instance/spi0.h"
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#include "instance/spi1.h"
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#include "instance/tc0.h"
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#include "instance/tc1.h"
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#include "instance/tc2.h"
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#include "instance/twi0.h"
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#include "instance/twi1.h"
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#include "instance/pwm.h"
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#include "instance/usart0.h"
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#include "instance/usart1.h"
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#include "instance/usart2.h"
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#include "instance/usart3.h"
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#include "instance/uotghs.h"
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#include "instance/emac.h"
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#include "instance/can0.h"
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#include "instance/can1.h"
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#include "instance/trng.h"
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#include "instance/adc.h"
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#include "instance/dmac.h"
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#include "instance/dacc.h"
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#include "instance/smc.h"
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#include "instance/sdramc.h"
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#include "instance/matrix.h"
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#include "instance/pmc.h"
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#include "instance/uart.h"
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#include "instance/chipid.h"
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#include "instance/efc0.h"
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#include "instance/efc1.h"
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#include "instance/pioa.h"
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#include "instance/piob.h"
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#include "instance/pioc.h"
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#include "instance/piod.h"
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#include "instance/pioe.h"
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#include "instance/piof.h"
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#include "instance/rstc.h"
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#include "instance/supc.h"
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#include "instance/rtt.h"
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#include "instance/wdt.h"
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#include "instance/rtc.h"
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#include "instance/gpbr.h"
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/*@}*/
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/* ************************************************************************** */
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/* PERIPHERAL ID DEFINITIONS FOR SAM3X8G */
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/* ************************************************************************** */
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/** \addtogroup SAM3X8G_id Peripheral Ids Definitions */
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/*@{*/
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#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
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#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
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#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
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#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
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#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
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#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
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#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
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#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
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#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
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#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
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#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */
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#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */
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#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
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#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
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#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */
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#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */
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#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */
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#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
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#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
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#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
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#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
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#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */
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#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */
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#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */
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#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */
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#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */
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#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */
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#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */
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#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */
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#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */
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#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */
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#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */
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#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */
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#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */
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#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */
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#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */
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#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */
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#define ID_ADC (37) /**< \brief ADC Controller (ADC) */
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#define ID_DACC (38) /**< \brief DAC Controller (DACC) */
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#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */
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#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
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#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */
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#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */
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#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */
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#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */
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/*@}*/
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/* ************************************************************************** */
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/* BASE ADDRESS DEFINITIONS FOR SAM3X8G */
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/* ************************************************************************** */
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/** \addtogroup SAM3X8G_base Peripheral Base Address Definitions */
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/*@{*/
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#ifdef __ASSEMBLY__
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#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
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#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
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#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
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#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */
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#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */
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#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */
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#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */
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#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */
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#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */
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#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */
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#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */
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#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */
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#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */
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#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */
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#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
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#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */
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#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
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#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */
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#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
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#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */
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#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
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#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */
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#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */
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#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */
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#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */
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#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */
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#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */
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#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */
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#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */
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#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */
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#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */
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#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */
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#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */
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#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */
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#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
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#define UART (0x400E0800U) /**< \brief (UART ) Base Address */
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#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */
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#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */
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#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */
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#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */
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#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
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#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
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#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
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#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
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#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
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#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */
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#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */
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#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */
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#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */
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#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */
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#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */
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#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */
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#else
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#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
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#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
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#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
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#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */
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#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */
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#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */
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#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */
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#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */
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#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */
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#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */
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#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */
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#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */
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#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */
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#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */
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#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
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#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */
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#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
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#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */
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#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
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#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */
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#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
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#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */
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#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */
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#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */
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#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */
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#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */
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#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */
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#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */
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#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */
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#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */
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#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */
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#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */
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#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */
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#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */
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#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
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#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */
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#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */
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#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */
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#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */
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#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */
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#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
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#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
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#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
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#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
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#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
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#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */
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#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */
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#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */
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#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */
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#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */
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#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */
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#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */
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#endif /* __ASSEMBLY__ */
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/*@}*/
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/* ************************************************************************** */
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/* PIO DEFINITIONS FOR SAM3X8G */
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/* ************************************************************************** */
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/** \addtogroup SAM3X8G_pio Peripheral Pio Definitions */
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/*@{*/
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#include "pio/sam3x8g.h"
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/*@}*/
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/* ************************************************************************** */
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/* MEMORY MAPPING DEFINITIONS FOR SAM3X8G */
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/* ************************************************************************** */
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#define IFLASH0_SIZE (0x40000u)
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#define IFLASH0_PAGE_SIZE (256u)
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#define IFLASH0_LOCK_REGION_SIZE (16384u)
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#define IFLASH0_NB_OF_PAGES (1024u)
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#define IFLASH1_SIZE (0x40000u)
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#define IFLASH1_PAGE_SIZE (256u)
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#define IFLASH1_LOCK_REGION_SIZE (16384u)
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#define IFLASH1_NB_OF_PAGES (1024u)
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#define IRAM0_SIZE (0x10000u)
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#define IRAM1_SIZE (0x8000u)
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#define NFCRAM_SIZE (0x1000u)
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#define IFLASH_SIZE (0x80000u)
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#define IRAM_SIZE (0x18000u)
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#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
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#if defined IFLASH0_SIZE
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#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
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#endif
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#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */
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#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
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#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
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#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
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#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
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#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
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#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
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#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
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#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
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#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */
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#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */
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#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */
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#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif /* _SAM3X8G_ */
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