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130 lines
9.1 KiB
C
130 lines
9.1 KiB
C
/* $asf_license$ */
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#ifndef _SAM3N_DACC_COMPONENT_
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#define _SAM3N_DACC_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
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/* ============================================================================= */
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/** \addtogroup SAM3N_DACC Digital-to-Analog Converter Controller */
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/*@{*/
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#ifndef __ASSEMBLY__
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/** \brief Dacc hardware registers */
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typedef struct {
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WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
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RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
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WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x08) Conversion Data Register */
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WoReg DACC_IER; /**< \brief (Dacc Offset: 0x0C) Interrupt Enable Register */
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WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x10) Interrupt Disable Register */
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RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x14) Interrupt Mask Register */
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RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x18) Interrupt Status Register */
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RoReg Reserved1[50];
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RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode Register */
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RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status Register */
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RoReg Reserved2[5];
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RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
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RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
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RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
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RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
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RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
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RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
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RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
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RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
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WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
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RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
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} Dacc;
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#endif /* __ASSEMBLY__ */
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/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
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#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
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/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
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#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
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#define DACC_MR_TRGSEL_Pos 1
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#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
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#define DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /**< \brief (DACC_MR) External trigger */
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#define DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 0 */
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#define DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 1 */
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#define DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 2 */
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#define DACC_MR_DACEN (0x1u << 4) /**< \brief (DACC_MR) DAC enable */
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#define DACC_MR_WORD (0x1u << 5) /**< \brief (DACC_MR) Word Transfer */
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#define DACC_MR_STARTUP_Pos 8
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#define DACC_MR_STARTUP_Msk (0xffu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
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#define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos)))
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#define DACC_MR_CLKDIV_Pos 16
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#define DACC_MR_CLKDIV_Msk (0xffffu << DACC_MR_CLKDIV_Pos) /**< \brief (DACC_MR) DAC Clock Divider for Internal Trigger */
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#define DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos)))
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/* -------- DACC_CDR : (DACC Offset: 0x08) Conversion Data Register -------- */
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#define DACC_CDR_DATA_Pos 0
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#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
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#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
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/* -------- DACC_IER : (DACC Offset: 0x0C) Interrupt Enable Register -------- */
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#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmission Ready Interrupt Enable */
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#define DACC_IER_ENDTX (0x1u << 1) /**< \brief (DACC_IER) End of PDC Interrupt Enable */
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#define DACC_IER_TXBUFE (0x1u << 2) /**< \brief (DACC_IER) Buffer Empty Interrupt Enable */
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/* -------- DACC_IDR : (DACC Offset: 0x10) Interrupt Disable Register -------- */
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#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmission Ready Interrupt Disable */
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#define DACC_IDR_ENDTX (0x1u << 1) /**< \brief (DACC_IDR) End of PDC Interrupt Disable */
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#define DACC_IDR_TXBUFE (0x1u << 2) /**< \brief (DACC_IDR) Buffer Empty Interrupt Disable */
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/* -------- DACC_IMR : (DACC Offset: 0x14) Interrupt Mask Register -------- */
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#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmission Ready Interrupt Mask */
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#define DACC_IMR_ENDTX (0x1u << 1) /**< \brief (DACC_IMR) End of PDC Interrupt Mask */
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#define DACC_IMR_TXBUFE (0x1u << 2) /**< \brief (DACC_IMR) Buffer Empty Interrupt Mask */
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/* -------- DACC_ISR : (DACC Offset: 0x18) Interrupt Status Register -------- */
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#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmission Ready Interrupt Flag */
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#define DACC_ISR_ENDTX (0x1u << 1) /**< \brief (DACC_ISR) End of PDC Interrupt Flag */
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#define DACC_ISR_TXBUFE (0x1u << 2) /**< \brief (DACC_ISR) Buffer Empty Interrupt Flag */
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/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode Register -------- */
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#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
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#define DACC_WPMR_WPKEY_Pos 8
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#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
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#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
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/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status Register -------- */
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#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
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#define DACC_WPSR_WPROTADDR_Pos 8
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#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
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/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
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#define DACC_RPR_RXPTR_Pos 0
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#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
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#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
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/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
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#define DACC_RCR_RXCTR_Pos 0
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#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
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#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
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/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
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#define DACC_TPR_TXPTR_Pos 0
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#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
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#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
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/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
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#define DACC_TCR_TXCTR_Pos 0
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#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
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#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
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/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
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#define DACC_RNPR_RXNPTR_Pos 0
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#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
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#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
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/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
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#define DACC_RNCR_RXNCTR_Pos 0
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#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
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#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
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/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
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#define DACC_TNPR_TXNPTR_Pos 0
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#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
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#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
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/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
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#define DACC_TNCR_TXNCTR_Pos 0
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#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
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#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
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/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
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#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
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#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
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#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
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#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
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/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
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#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
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#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
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/*@}*/
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#endif /* _SAM3N_DACC_COMPONENT_ */
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