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54 lines
4.0 KiB
C
54 lines
4.0 KiB
C
/* $asf_license$ */
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#ifndef _SAM3U_ADC_INSTANCE_
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#define _SAM3U_ADC_INSTANCE_
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/* ========== Register definition for ADC peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_ADC_CR (0x400AC000U) /**< \brief (ADC) Control Register */
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#define REG_ADC_MR (0x400AC004U) /**< \brief (ADC) Mode Register */
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#define REG_ADC_CHER (0x400AC010U) /**< \brief (ADC) Channel Enable Register */
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#define REG_ADC_CHDR (0x400AC014U) /**< \brief (ADC) Channel Disable Register */
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#define REG_ADC_CHSR (0x400AC018U) /**< \brief (ADC) Channel Status Register */
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#define REG_ADC_SR (0x400AC01CU) /**< \brief (ADC) Status Register */
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#define REG_ADC_LCDR (0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
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#define REG_ADC_IER (0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
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#define REG_ADC_IDR (0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
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#define REG_ADC_IMR (0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
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#define REG_ADC_CDR (0x400AC030U) /**< \brief (ADC) Channel Data Register */
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#define REG_ADC_RPR (0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
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#define REG_ADC_RCR (0x400AC104U) /**< \brief (ADC) Receive Counter Register */
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#define REG_ADC_TPR (0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
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#define REG_ADC_TCR (0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
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#define REG_ADC_RNPR (0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
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#define REG_ADC_RNCR (0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
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#define REG_ADC_TNPR (0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
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#define REG_ADC_TNCR (0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
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#define REG_ADC_PTCR (0x400AC120U) /**< \brief (ADC) Transfer Control Register */
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#define REG_ADC_PTSR (0x400AC124U) /**< \brief (ADC) Transfer Status Register */
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#else
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#define REG_ADC_CR (*(WoReg*)0x400AC000U) /**< \brief (ADC) Control Register */
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#define REG_ADC_MR (*(RwReg*)0x400AC004U) /**< \brief (ADC) Mode Register */
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#define REG_ADC_CHER (*(WoReg*)0x400AC010U) /**< \brief (ADC) Channel Enable Register */
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#define REG_ADC_CHDR (*(WoReg*)0x400AC014U) /**< \brief (ADC) Channel Disable Register */
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#define REG_ADC_CHSR (*(RoReg*)0x400AC018U) /**< \brief (ADC) Channel Status Register */
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#define REG_ADC_SR (*(RoReg*)0x400AC01CU) /**< \brief (ADC) Status Register */
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#define REG_ADC_LCDR (*(RoReg*)0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
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#define REG_ADC_IER (*(WoReg*)0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
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#define REG_ADC_IDR (*(WoReg*)0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
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#define REG_ADC_IMR (*(RoReg*)0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
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#define REG_ADC_CDR (*(RoReg*)0x400AC030U) /**< \brief (ADC) Channel Data Register */
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#define REG_ADC_RPR (*(RwReg*)0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
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#define REG_ADC_RCR (*(RwReg*)0x400AC104U) /**< \brief (ADC) Receive Counter Register */
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#define REG_ADC_TPR (*(RwReg*)0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
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#define REG_ADC_TCR (*(RwReg*)0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
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#define REG_ADC_RNPR (*(RwReg*)0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
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#define REG_ADC_RNCR (*(RwReg*)0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
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#define REG_ADC_TNPR (*(RwReg*)0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
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#define REG_ADC_TNCR (*(RwReg*)0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
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#define REG_ADC_PTCR (*(WoReg*)0x400AC120U) /**< \brief (ADC) Transfer Control Register */
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#define REG_ADC_PTSR (*(RoReg*)0x400AC124U) /**< \brief (ADC) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3U_ADC_INSTANCE_ */
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