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54 lines
4.1 KiB
C
54 lines
4.1 KiB
C
/* $asf_license$ */
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#ifndef _SAM3U_PMC_INSTANCE_
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#define _SAM3U_PMC_INSTANCE_
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/* ========== Register definition for PMC peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
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#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
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#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
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#define REG_PMC_PCER (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
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#define REG_PMC_PCDR (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
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#define REG_PMC_PCSR (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
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#define REG_CKGR_UCKR (0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
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#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
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#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
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#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */
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#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */
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#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
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#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
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#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
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#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */
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#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
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#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
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#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
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#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
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#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
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#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
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#else
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#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
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#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
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#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
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#define REG_PMC_PCER (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
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#define REG_PMC_PCDR (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
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#define REG_PMC_PCSR (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
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#define REG_CKGR_UCKR (*(RwReg*)0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
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#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
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#define REG_CKGR_MCFR (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
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#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
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#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
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#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
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#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
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#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
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#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
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#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
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#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
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#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
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#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
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#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
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#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3U_PMC_INSTANCE_ */
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