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54 lines
4.0 KiB
C
54 lines
4.0 KiB
C
/* $asf_license$ */
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#ifndef _SAM3U_TWI0_INSTANCE_
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#define _SAM3U_TWI0_INSTANCE_
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/* ========== Register definition for TWI0 peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_TWI0_CR (0x40084000U) /**< \brief (TWI0) Control Register */
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#define REG_TWI0_MMR (0x40084004U) /**< \brief (TWI0) Master Mode Register */
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#define REG_TWI0_SMR (0x40084008U) /**< \brief (TWI0) Slave Mode Register */
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#define REG_TWI0_IADR (0x4008400CU) /**< \brief (TWI0) Internal Address Register */
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#define REG_TWI0_CWGR (0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
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#define REG_TWI0_SR (0x40084020U) /**< \brief (TWI0) Status Register */
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#define REG_TWI0_IER (0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
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#define REG_TWI0_IDR (0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
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#define REG_TWI0_IMR (0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
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#define REG_TWI0_RHR (0x40084030U) /**< \brief (TWI0) Receive Holding Register */
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#define REG_TWI0_THR (0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
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#define REG_TWI0_RPR (0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
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#define REG_TWI0_RCR (0x40084104U) /**< \brief (TWI0) Receive Counter Register */
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#define REG_TWI0_TPR (0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
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#define REG_TWI0_TCR (0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
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#define REG_TWI0_RNPR (0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
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#define REG_TWI0_RNCR (0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
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#define REG_TWI0_TNPR (0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
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#define REG_TWI0_TNCR (0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
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#define REG_TWI0_PTCR (0x40084120U) /**< \brief (TWI0) Transfer Control Register */
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#define REG_TWI0_PTSR (0x40084124U) /**< \brief (TWI0) Transfer Status Register */
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#else
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#define REG_TWI0_CR (*(WoReg*)0x40084000U) /**< \brief (TWI0) Control Register */
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#define REG_TWI0_MMR (*(RwReg*)0x40084004U) /**< \brief (TWI0) Master Mode Register */
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#define REG_TWI0_SMR (*(RwReg*)0x40084008U) /**< \brief (TWI0) Slave Mode Register */
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#define REG_TWI0_IADR (*(RwReg*)0x4008400CU) /**< \brief (TWI0) Internal Address Register */
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#define REG_TWI0_CWGR (*(RwReg*)0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
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#define REG_TWI0_SR (*(RoReg*)0x40084020U) /**< \brief (TWI0) Status Register */
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#define REG_TWI0_IER (*(WoReg*)0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
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#define REG_TWI0_IDR (*(WoReg*)0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
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#define REG_TWI0_IMR (*(RoReg*)0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
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#define REG_TWI0_RHR (*(RoReg*)0x40084030U) /**< \brief (TWI0) Receive Holding Register */
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#define REG_TWI0_THR (*(WoReg*)0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
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#define REG_TWI0_RPR (*(RwReg*)0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
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#define REG_TWI0_RCR (*(RwReg*)0x40084104U) /**< \brief (TWI0) Receive Counter Register */
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#define REG_TWI0_TPR (*(RwReg*)0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
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#define REG_TWI0_TCR (*(RwReg*)0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
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#define REG_TWI0_RNPR (*(RwReg*)0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
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#define REG_TWI0_RNCR (*(RwReg*)0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
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#define REG_TWI0_TNPR (*(RwReg*)0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
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#define REG_TWI0_TNCR (*(RwReg*)0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
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#define REG_TWI0_PTCR (*(WoReg*)0x40084120U) /**< \brief (TWI0) Transfer Control Register */
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#define REG_TWI0_PTSR (*(RoReg*)0x40084124U) /**< \brief (TWI0) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3U_TWI0_INSTANCE_ */
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