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54 lines
4.0 KiB
C
54 lines
4.0 KiB
C
/* $asf_license$ */
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#ifndef _SAM3U_TWI1_INSTANCE_
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#define _SAM3U_TWI1_INSTANCE_
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/* ========== Register definition for TWI1 peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_TWI1_CR (0x40088000U) /**< \brief (TWI1) Control Register */
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#define REG_TWI1_MMR (0x40088004U) /**< \brief (TWI1) Master Mode Register */
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#define REG_TWI1_SMR (0x40088008U) /**< \brief (TWI1) Slave Mode Register */
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#define REG_TWI1_IADR (0x4008800CU) /**< \brief (TWI1) Internal Address Register */
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#define REG_TWI1_CWGR (0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
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#define REG_TWI1_SR (0x40088020U) /**< \brief (TWI1) Status Register */
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#define REG_TWI1_IER (0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
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#define REG_TWI1_IDR (0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
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#define REG_TWI1_IMR (0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
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#define REG_TWI1_RHR (0x40088030U) /**< \brief (TWI1) Receive Holding Register */
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#define REG_TWI1_THR (0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
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#define REG_TWI1_RPR (0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
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#define REG_TWI1_RCR (0x40088104U) /**< \brief (TWI1) Receive Counter Register */
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#define REG_TWI1_TPR (0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
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#define REG_TWI1_TCR (0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
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#define REG_TWI1_RNPR (0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
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#define REG_TWI1_RNCR (0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
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#define REG_TWI1_TNPR (0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
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#define REG_TWI1_TNCR (0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
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#define REG_TWI1_PTCR (0x40088120U) /**< \brief (TWI1) Transfer Control Register */
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#define REG_TWI1_PTSR (0x40088124U) /**< \brief (TWI1) Transfer Status Register */
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#else
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#define REG_TWI1_CR (*(WoReg*)0x40088000U) /**< \brief (TWI1) Control Register */
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#define REG_TWI1_MMR (*(RwReg*)0x40088004U) /**< \brief (TWI1) Master Mode Register */
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#define REG_TWI1_SMR (*(RwReg*)0x40088008U) /**< \brief (TWI1) Slave Mode Register */
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#define REG_TWI1_IADR (*(RwReg*)0x4008800CU) /**< \brief (TWI1) Internal Address Register */
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#define REG_TWI1_CWGR (*(RwReg*)0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
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#define REG_TWI1_SR (*(RoReg*)0x40088020U) /**< \brief (TWI1) Status Register */
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#define REG_TWI1_IER (*(WoReg*)0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
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#define REG_TWI1_IDR (*(WoReg*)0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
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#define REG_TWI1_IMR (*(RoReg*)0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
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#define REG_TWI1_RHR (*(RoReg*)0x40088030U) /**< \brief (TWI1) Receive Holding Register */
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#define REG_TWI1_THR (*(WoReg*)0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
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#define REG_TWI1_RPR (*(RwReg*)0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
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#define REG_TWI1_RCR (*(RwReg*)0x40088104U) /**< \brief (TWI1) Receive Counter Register */
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#define REG_TWI1_TPR (*(RwReg*)0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
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#define REG_TWI1_TCR (*(RwReg*)0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
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#define REG_TWI1_RNPR (*(RwReg*)0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
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#define REG_TWI1_RNCR (*(RwReg*)0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
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#define REG_TWI1_TNPR (*(RwReg*)0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
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#define REG_TWI1_TNCR (*(RwReg*)0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
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#define REG_TWI1_PTCR (*(WoReg*)0x40088120U) /**< \brief (TWI1) Transfer Control Register */
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#define REG_TWI1_PTSR (*(RoReg*)0x40088124U) /**< \brief (TWI1) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3U_TWI1_INSTANCE_ */
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