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66 lines
5.3 KiB
C
66 lines
5.3 KiB
C
/* $asf_license$ */
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#ifndef _SAM3U_USART3_INSTANCE_
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#define _SAM3U_USART3_INSTANCE_
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/* ========== Register definition for USART3 peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_USART3_CR (0x4009C000U) /**< \brief (USART3) Control Register */
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#define REG_USART3_MR (0x4009C004U) /**< \brief (USART3) Mode Register */
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#define REG_USART3_IER (0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
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#define REG_USART3_IDR (0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
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#define REG_USART3_IMR (0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
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#define REG_USART3_CSR (0x4009C014U) /**< \brief (USART3) Channel Status Register */
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#define REG_USART3_RHR (0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
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#define REG_USART3_THR (0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
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#define REG_USART3_BRGR (0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
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#define REG_USART3_RTOR (0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
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#define REG_USART3_TTGR (0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
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#define REG_USART3_FIDI (0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
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#define REG_USART3_NER (0x4009C044U) /**< \brief (USART3) Number of Errors Register */
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#define REG_USART3_IF (0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
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#define REG_USART3_MAN (0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
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#define REG_USART3_WPMR (0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
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#define REG_USART3_WPSR (0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
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#define REG_USART3_RPR (0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
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#define REG_USART3_RCR (0x4009C104U) /**< \brief (USART3) Receive Counter Register */
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#define REG_USART3_TPR (0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
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#define REG_USART3_TCR (0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
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#define REG_USART3_RNPR (0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
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#define REG_USART3_RNCR (0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
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#define REG_USART3_TNPR (0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
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#define REG_USART3_TNCR (0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
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#define REG_USART3_PTCR (0x4009C120U) /**< \brief (USART3) Transfer Control Register */
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#define REG_USART3_PTSR (0x4009C124U) /**< \brief (USART3) Transfer Status Register */
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#else
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#define REG_USART3_CR (*(WoReg*)0x4009C000U) /**< \brief (USART3) Control Register */
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#define REG_USART3_MR (*(RwReg*)0x4009C004U) /**< \brief (USART3) Mode Register */
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#define REG_USART3_IER (*(WoReg*)0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
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#define REG_USART3_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
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#define REG_USART3_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
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#define REG_USART3_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART3) Channel Status Register */
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#define REG_USART3_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
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#define REG_USART3_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
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#define REG_USART3_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
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#define REG_USART3_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
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#define REG_USART3_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
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#define REG_USART3_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
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#define REG_USART3_NER (*(RoReg*)0x4009C044U) /**< \brief (USART3) Number of Errors Register */
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#define REG_USART3_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
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#define REG_USART3_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
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#define REG_USART3_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
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#define REG_USART3_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
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#define REG_USART3_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
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#define REG_USART3_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART3) Receive Counter Register */
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#define REG_USART3_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
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#define REG_USART3_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
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#define REG_USART3_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
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#define REG_USART3_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
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#define REG_USART3_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
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#define REG_USART3_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
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#define REG_USART3_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART3) Transfer Control Register */
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#define REG_USART3_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART3) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3U_USART3_INSTANCE_ */
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