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52 lines
4.7 KiB
C
52 lines
4.7 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3XA_PIOF_INSTANCE_
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#define _SAM3XA_PIOF_INSTANCE_
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/* ========== Register definition for PIOF peripheral ========== */
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#define REG_PIOF_PER REG_ACCESS(WoReg, 0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
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#define REG_PIOF_PDR REG_ACCESS(WoReg, 0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
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#define REG_PIOF_PSR REG_ACCESS(RoReg, 0x400E1808U) /**< \brief (PIOF) PIO Status Register */
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#define REG_PIOF_OER REG_ACCESS(WoReg, 0x400E1810U) /**< \brief (PIOF) Output Enable Register */
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#define REG_PIOF_ODR REG_ACCESS(WoReg, 0x400E1814U) /**< \brief (PIOF) Output Disable Register */
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#define REG_PIOF_OSR REG_ACCESS(RoReg, 0x400E1818U) /**< \brief (PIOF) Output Status Register */
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#define REG_PIOF_IFER REG_ACCESS(WoReg, 0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
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#define REG_PIOF_IFDR REG_ACCESS(WoReg, 0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
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#define REG_PIOF_IFSR REG_ACCESS(RoReg, 0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
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#define REG_PIOF_SODR REG_ACCESS(WoReg, 0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
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#define REG_PIOF_CODR REG_ACCESS(WoReg, 0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
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#define REG_PIOF_ODSR REG_ACCESS(RwReg, 0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
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#define REG_PIOF_PDSR REG_ACCESS(RoReg, 0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
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#define REG_PIOF_IER REG_ACCESS(WoReg, 0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
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#define REG_PIOF_IDR REG_ACCESS(WoReg, 0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
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#define REG_PIOF_IMR REG_ACCESS(RoReg, 0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
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#define REG_PIOF_ISR REG_ACCESS(RoReg, 0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
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#define REG_PIOF_MDER REG_ACCESS(WoReg, 0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
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#define REG_PIOF_MDDR REG_ACCESS(WoReg, 0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
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#define REG_PIOF_MDSR REG_ACCESS(RoReg, 0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
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#define REG_PIOF_PUDR REG_ACCESS(WoReg, 0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
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#define REG_PIOF_PUER REG_ACCESS(WoReg, 0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
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#define REG_PIOF_PUSR REG_ACCESS(RoReg, 0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
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#define REG_PIOF_ABSR REG_ACCESS(RwReg, 0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
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#define REG_PIOF_SCIFSR REG_ACCESS(WoReg, 0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
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#define REG_PIOF_DIFSR REG_ACCESS(WoReg, 0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
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#define REG_PIOF_IFDGSR REG_ACCESS(RoReg, 0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
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#define REG_PIOF_SCDR REG_ACCESS(RwReg, 0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
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#define REG_PIOF_OWER REG_ACCESS(WoReg, 0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
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#define REG_PIOF_OWDR REG_ACCESS(WoReg, 0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
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#define REG_PIOF_OWSR REG_ACCESS(RoReg, 0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
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#define REG_PIOF_AIMER REG_ACCESS(WoReg, 0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
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#define REG_PIOF_AIMDR REG_ACCESS(WoReg, 0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
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#define REG_PIOF_AIMMR REG_ACCESS(RoReg, 0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
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#define REG_PIOF_ESR REG_ACCESS(WoReg, 0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
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#define REG_PIOF_LSR REG_ACCESS(WoReg, 0x400E18C4U) /**< \brief (PIOF) Level Select Register */
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#define REG_PIOF_ELSR REG_ACCESS(RoReg, 0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
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#define REG_PIOF_FELLSR REG_ACCESS(WoReg, 0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
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#define REG_PIOF_REHLSR REG_ACCESS(WoReg, 0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
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#define REG_PIOF_FRLHSR REG_ACCESS(RoReg, 0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
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#define REG_PIOF_LOCKSR REG_ACCESS(RoReg, 0x400E18E0U) /**< \brief (PIOF) Lock Status */
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#define REG_PIOF_WPMR REG_ACCESS(RwReg, 0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
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#define REG_PIOF_WPSR REG_ACCESS(RoReg, 0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
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#endif /* _SAM3XA_PIOF_INSTANCE_ */
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