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403 lines
10 KiB
C
403 lines
10 KiB
C
/**
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* \file
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*
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* \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM.
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*
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* Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include "../chip.h"
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#include <string.h>
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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/**
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* \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC)
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*
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* The Enhanced Embedded Flash Controller ensures the interface of the Flash block with
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* the 32-bit internal bus.
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*
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* @{
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*/
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/* Address definition for read operation */
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#if (SAM3XA_SERIES || SAM3U_SERIES /*|| SAM4SD16 || SAM4SD32*/)
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# define READ_BUFF_ADDR0 IFLASH0_ADDR
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# define READ_BUFF_ADDR1 IFLASH1_ADDR
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#elif (SAM3S_SERIES || SAM3N_SERIES)
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# define READ_BUFF_ADDR IFLASH_ADDR
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#elif (SAM3U_SERIES || SAM4S_SERIES)
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# define READ_BUFF_ADDR IFLASH0_ADDR
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#else
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# warning Only reading unique id for sam3 is implemented.
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#endif
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/* Flash Writing Protection Key */
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#define FWP_KEY 0x5Au
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#if SAM4S_SERIES
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#define EEFC_FCR_FCMD(value) \
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((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
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#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR)
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#else
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#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)
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#endif
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/*
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* Local function declaration.
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* Because they are RAM functions, they need 'extern' declaration.
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*/
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extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr);
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extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr);
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/**
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* \brief Initialize the EFC controller.
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*
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* \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit.
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* \param ul_fws The number of wait states in cycle (no shift).
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*
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* \return 0 if successful.
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*/
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uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws)
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{
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efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws));
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return EFC_RC_OK;
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}
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/**
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* \brief Enable the flash ready interrupt.
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*
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* \param p_efc Pointer to an EFC instance.
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*/
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void efc_enable_frdy_interrupt(Efc *p_efc)
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{
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uint32_t ul_fmr = p_efc->EEFC_FMR;
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efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY);
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}
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/**
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* \brief Disable the flash ready interrupt.
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*
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* \param p_efc Pointer to an EFC instance.
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*/
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void efc_disable_frdy_interrupt(Efc *p_efc)
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{
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uint32_t ul_fmr = p_efc->EEFC_FMR;
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efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY));
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}
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/**
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* \brief Set flash access mode.
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*
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* \param p_efc Pointer to an EFC instance.
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* \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit.
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*/
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void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode)
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{
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uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM);
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efc_write_fmr(p_efc, ul_fmr | ul_mode);
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}
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/**
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* \brief Get flash access mode.
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*
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* \param p_efc Pointer to an EFC instance.
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*
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* \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit.
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*/
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uint32_t efc_get_flash_access_mode(Efc *p_efc)
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{
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return (p_efc->EEFC_FMR & EEFC_FMR_FAM);
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}
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/**
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* \brief Set flash wait state.
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*
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* \param p_efc Pointer to an EFC instance.
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* \param ul_fws The number of wait states in cycle (no shift).
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*/
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void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws)
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{
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uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk);
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efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws));
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}
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/**
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* \brief Get flash wait state.
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*
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* \param p_efc Pointer to an EFC instance.
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*
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* \return The number of wait states in cycle (no shift).
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*/
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uint32_t efc_get_wait_state(Efc *p_efc)
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{
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return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos);
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}
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/**
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* \brief Perform the given command and wait until its completion (or an error).
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*
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* \note Unique ID commands are not supported, use efc_read_unique_id.
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*
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* \param p_efc Pointer to an EFC instance.
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* \param ul_command Command to perform.
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* \param ul_argument Optional command argument.
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*
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* \note This function will automatically choose to use IAP function.
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*
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* \return 0 if successful, otherwise returns an error code.
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*/
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uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command,
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uint32_t ul_argument)
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{
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// Unique ID commands are not supported.
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if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) {
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return EFC_RC_NOT_SUPPORT;
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}
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#if (SAM3XA_SERIES || SAM3U4)
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// Use IAP function with 2 parameters in ROM.
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static uint32_t(*iap_perform_command) (uint32_t, uint32_t);
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uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1;
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iap_perform_command =
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(uint32_t(*)(uint32_t, uint32_t))
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*((uint32_t *) CHIP_FLASH_IAP_ADDRESS);
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iap_perform_command(ul_efc_nb,
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EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
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EEFC_FCR_FCMD(ul_command));
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return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS);
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#elif (SAM3N_SERIES || SAM3S_SERIES || SAM4S_SERIES || SAM3U_SERIES)
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// Use IAP function with 2 parameter in ROM.
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static uint32_t(*iap_perform_command) (uint32_t, uint32_t);
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iap_perform_command =
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(uint32_t(*)(uint32_t, uint32_t))
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*((uint32_t *) CHIP_FLASH_IAP_ADDRESS);
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#if SAM4S_SERIES
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uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1;
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iap_perform_command(ul_efc_nb,
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EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) |
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EEFC_FCR_FCMD(ul_command));
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#else
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iap_perform_command(0,
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EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
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EEFC_FCR_FCMD(ul_command));
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#endif
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return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS);
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#else
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// Use RAM Function.
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return efc_perform_fcr(p_efc,
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EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
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EEFC_FCR_FCMD(ul_command));
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#endif
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}
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/**
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* \brief Get the current status of the EEFC.
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*
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* \note This function clears the value of some status bits (FLOCKE, FCMDE).
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*
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* \param p_efc Pointer to an EFC instance.
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*
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* \return The current status.
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*/
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uint32_t efc_get_status(Efc *p_efc)
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{
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return p_efc->EEFC_FSR;
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}
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/**
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* \brief Get the result of the last executed command.
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*
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* \param p_efc Pointer to an EFC instance.
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*
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* \return The result of the last executed command.
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*/
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uint32_t efc_get_result(Efc *p_efc)
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{
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return p_efc->EEFC_FRR;
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}
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/**
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* \brief Perform read sequence. Supported sequences are read Unique ID and
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* read User Signature
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*
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* \param p_efc Pointer to an EFC instance.
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* \param ul_cmd_st Start command to perform.
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* \param ul_cmd_sp Stop command to perform.
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* \param p_ul_buf Pointer to an data buffer.
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* \param ul_size Buffer size.
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*
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* \return 0 if successful, otherwise returns an error code.
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*/
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#ifdef __ICCARM__
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__ramfunc
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#else
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__attribute__ ((section(".ramfunc")))
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#endif
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uint32_t efc_perform_read_sequence(Efc *p_efc,
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uint32_t ul_cmd_st, uint32_t ul_cmd_sp,
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uint32_t *p_ul_buf, uint32_t ul_size)
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{
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volatile uint32_t ul_status;
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uint32_t ul_cnt;
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#if (SAM3U4 || SAM3XA_SERIES /*|| SAM4SD16 || SAM4SD32*/)
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uint32_t *p_ul_data =
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(uint32_t *) ((p_efc == EFC0) ?
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READ_BUFF_ADDR0 : READ_BUFF_ADDR1);
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#elif (SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3U_SERIES)
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uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR;
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#else
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return EFC_RC_NOT_SUPPORT;
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#endif
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if (p_ul_buf == NULL) {
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return EFC_RC_INVALID;
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}
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p_efc->EEFC_FMR |= (0x1u << 16);
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/* Send the Start Read command */
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#if SAM4S_SERIES
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p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0)
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| EEFC_FCR_FCMD(ul_cmd_st);
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#else
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p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0)
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| EEFC_FCR_FCMD(ul_cmd_st);
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#endif
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/* Wait for the FRDY bit in the Flash Programming Status Register
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* (EEFC_FSR) falls.
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*/
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do {
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ul_status = p_efc->EEFC_FSR;
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} while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);
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/* The data is located in the first address of the Flash
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* memory mapping.
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*/
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for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) {
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p_ul_buf[ul_cnt] = p_ul_data[ul_cnt];
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}
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/* To stop the read mode */
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p_efc->EEFC_FCR =
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#if SAM4S_SERIES
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EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) |
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EEFC_FCR_FCMD(ul_cmd_sp);
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#else
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EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) |
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EEFC_FCR_FCMD(ul_cmd_sp);
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#endif
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/* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR)
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* rises.
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*/
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do {
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ul_status = p_efc->EEFC_FSR;
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} while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
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p_efc->EEFC_FMR &= ~(0x1u << 16);
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return EFC_RC_OK;
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}
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/**
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* \brief Set mode register.
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*
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* \param p_efc Pointer to an EFC instance.
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* \param ul_fmr Value of mode register
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*/
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#ifdef __ICCARM__
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__ramfunc
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#else
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__attribute__ ((section(".ramfunc")))
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#endif
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void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr)
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{
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p_efc->EEFC_FMR = ul_fmr;
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}
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/**
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* \brief Perform command.
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*
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* \param p_efc Pointer to an EFC instance.
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* \param ul_fcr Flash command.
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*
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* \return The current status.
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*/
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#ifdef __ICCARM__
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__ramfunc
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#else
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__attribute__ ((section(".ramfunc")))
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#endif
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uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr)
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{
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volatile uint32_t ul_status;
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p_efc->EEFC_FCR = ul_fcr;
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do {
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ul_status = p_efc->EEFC_FSR;
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} while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
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return (ul_status & EEFC_ERROR_FLAGS);
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}
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//@}
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/// @endcond
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