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249 lines
10 KiB
C
249 lines
10 KiB
C
/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011-2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef ADC_H_INCLUDED
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#define ADC_H_INCLUDED
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#include "../chip.h"
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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/* The max adc sample freq definition*/
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#define ADC_FREQ_MAX 20000000
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/* The min adc sample freq definition*/
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#define ADC_FREQ_MIN 1000000
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/* The normal adc startup time*/
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#define ADC_STARTUP_NORM 40
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/* The fast adc startup time*/
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#define ADC_STARTUP_FAST 12
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/* Definitions for ADC resolution */
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#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
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enum adc_resolution_t {
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ADC_10_BITS = ADC_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */
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ADC_12_BITS = ADC_MR_LOWRES_BITS_12 /* ADC 12-bit resolution */
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};
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#elif SAM3N_SERIES
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enum adc_resolution_t {
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ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */
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ADC_10_BITS = ADC_MR_LOWRES_BITS_10 /* ADC 10-bit resolution */
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} ;
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#elif SAM3U_SERIES
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enum adc_resolution_t {
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ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */
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ADC_10_BITS = ADC12B_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */
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ADC_12_BITS = ADC12B_MR_LOWRES_BITS_12 /* ADC 12-bit resolution */
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} ;
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#endif
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/* Definitions for ADC trigger */
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enum adc_trigger_t {
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ADC_TRIG_SW = ADC_MR_TRGEN_DIS, /* Starting a conversion is only possible by software. */
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ADC_TRIG_EXT = ((ADC_MR_TRGSEL_ADC_TRIG0 << ADC_MR_TRGSEL_Pos) &
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ADC_MR_TRGSEL_Msk) | ADC_MR_TRGEN, /* External trigger */
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ADC_TRIG_TIO_CH_0 = (ADC_MR_TRGSEL_ADC_TRIG1 & ADC_MR_TRGSEL_Msk) |
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ADC_MR_TRGEN, /* TIO Output of the Timer Counter Channel 0 */
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ADC_TRIG_TIO_CH_1 = (ADC_MR_TRGSEL_ADC_TRIG2 & ADC_MR_TRGSEL_Msk) |
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ADC_MR_TRGEN, /* TIO Output of the Timer Counter Channel 1 */
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ADC_TRIG_TIO_CH_2 = (ADC_MR_TRGSEL_ADC_TRIG3 & ADC_MR_TRGSEL_Msk) |
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ADC_MR_TRGEN, /* TIO Output of the Timer Counter Channel 2 */
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#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES || SAM3U_SERIES
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ADC_TRIG_PWM_EVENT_LINE_0 = (ADC_MR_TRGSEL_ADC_TRIG4 & ADC_MR_TRGSEL_Msk) |
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ADC_MR_TRGEN, /* PWM Event Line 0 */
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ADC_TRIG_PWM_EVENT_LINE_1 = (ADC_MR_TRGSEL_ADC_TRIG5 & ADC_MR_TRGSEL_Msk) |
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ADC_MR_TRGEN /* PWM Event Line 1 */
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#endif
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} ;
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#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
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/* Definitions for ADC channel number */
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enum adc_channel_num_t {
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ADC_CHANNEL_0 = 0,
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ADC_CHANNEL_1 = 1,
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ADC_CHANNEL_2 = 2,
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ADC_CHANNEL_3 = 3,
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ADC_CHANNEL_4 = 4,
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ADC_CHANNEL_5 = 5,
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ADC_CHANNEL_6 = 6,
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ADC_CHANNEL_7 = 7,
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ADC_CHANNEL_8 = 8,
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ADC_CHANNEL_9 = 9,
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ADC_CHANNEL_10 = 10,
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ADC_CHANNEL_11 = 11,
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ADC_CHANNEL_12 = 12,
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ADC_CHANNEL_13 = 13,
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ADC_CHANNEL_14 = 14,
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ADC_TEMPERATURE_SENSOR = 15,
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} ;
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#elif SAM3U_SERIES
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/* Definitions for ADC channel number */
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enum adc_channel_num_t {
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ADC_CHANNEL_0 = 0,
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ADC_CHANNEL_1 = 1,
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ADC_CHANNEL_2 = 2,
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ADC_CHANNEL_3 = 3,
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ADC_CHANNEL_4 = 4,
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ADC_CHANNEL_5 = 5,
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ADC_CHANNEL_6 = 6,
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ADC_CHANNEL_7 = 7,
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} ;
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#endif
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/* Definitions for ADC gain value */
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enum adc_gainvalue_t{
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ADC_GAINVALUE_0 = 0,
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ADC_GAINVALUE_1 = 1,
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ADC_GAINVALUE_2 = 2,
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ADC_GAINVALUE_3 = 3
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};
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/* Definitions for ADC analog settling time */
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#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
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enum adc_settling_time_t{
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ADC_SETTLING_TIME_0 = ADC_MR_SETTLING_AST3,
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ADC_SETTLING_TIME_1 = ADC_MR_SETTLING_AST5,
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ADC_SETTLING_TIME_2 = ADC_MR_SETTLING_AST9,
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ADC_SETTLING_TIME_3 = ADC_MR_SETTLING_AST17
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};
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#endif
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#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
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uint32_t adc_init(Adc *p_adc, const uint32_t ul_mck,
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const uint32_t ul_adc_clock, const uint8_t uc_startup);
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void adc_configure_trigger(Adc *p_adc, const enum adc_trigger_t trigger,
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const uint8_t uc_freerun);
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void adc_configure_power_save(Adc *p_adc, const uint8_t uc_sleep, const uint8_t uc_fwup);
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void adc_configure_sequence(Adc *p_adc, const enum adc_channel_num_t ch_list[],
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const uint8_t uc_num);
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void adc_enable_tag(Adc *p_adc);
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void adc_disable_tag(Adc *p_adc);
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enum adc_channel_num_t adc_get_tag(const Adc *p_adc);
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void adc_start_sequencer(Adc *p_adc);
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void adc_stop_sequencer(Adc *p_adc);
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void adc_set_comparison_mode(Adc *p_adc, const uint8_t uc_mode);
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uint32_t adc_get_comparison_mode(const Adc *p_adc);
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void adc_set_comparison_window(Adc *p_adc, const uint16_t us_low_threshold,
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const uint16_t us_high_threshold);
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void adc_set_comparison_channel(Adc *p_adc, const enum adc_channel_num_t channel);
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void adc_set_writeprotect(Adc *p_adc, const uint32_t ul_enable);
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uint32_t adc_get_writeprotect_status(const Adc *p_adc);
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void adc_check(Adc* p_adc, const uint32_t ul_mck);
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uint32_t adc_get_overrun_status(const Adc *p_adc);
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#elif SAM3U_SERIES
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uint32_t adc_init(Adc * p_adc, const uint32_t ul_mck, const uint32_t ul_adc_clock,
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const uint32_t ul_startuptime);
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void adc_configure_trigger(Adc *p_adc, const enum adc_trigger_t trigger);
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void adc_configure_power_save(Adc *p_adc, const uint8_t uc_sleep);
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#endif
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void adc_set_resolution(Adc *p_adc, const enum adc_resolution_t resolution);
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void adc_start(Adc *p_adc);
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void adc_stop(Adc *p_adc);
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void adc_enable_channel(Adc *p_adc, const enum adc_channel_num_t adc_ch);
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void adc_disable_channel(Adc *p_adc, const enum adc_channel_num_t adc_ch);
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void adc_enable_all_channel(Adc *p_adc);
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void adc_disable_all_channel(Adc *p_adc);
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uint32_t adc_get_channel_status(const Adc *p_adc, const enum adc_channel_num_t adc_ch);
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uint32_t adc_get_channel_value(const Adc *p_adc,const enum adc_channel_num_t adc_ch);
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uint32_t adc_get_latest_value(const Adc *p_adc);
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uint32_t adc_get_actual_adc_clock(const Adc *p_adc, const uint32_t ul_mck);
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void adc_enable_interrupt(Adc *p_adc, const uint32_t ul_source);
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void adc_disable_interrupt(Adc *p_adc, const uint32_t ul_source);
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uint32_t adc_get_status(const Adc *p_adc);
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uint32_t adc_get_interrupt_mask(const Adc *p_adc);
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Pdc *adc_get_pdc_base(const Adc *p_adc);
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#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
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void adc_configure_timing(Adc *p_adc, const uint8_t uc_tracking,
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const enum adc_settling_time_t settling, const uint8_t uc_transfer);
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void adc_enable_anch( Adc *p_adc );
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void adc_disable_anch( Adc *p_adc );
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void adc_enable_channel_differential_input(Adc *p_adc, const enum adc_channel_num_t channel);
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void adc_disable_channel_differential_input(Adc *p_adc, const enum adc_channel_num_t channel);
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void adc_enable_channel_input_offset(Adc *p_adc, const enum adc_channel_num_t channel);
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void adc_disable_channel_input_offset(Adc *p_adc, const enum adc_channel_num_t channel);
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void adc_set_channel_input_gain(Adc *p_adc, const enum adc_channel_num_t channel,
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const enum adc_gainvalue_t uc_gain);
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void adc_set_bias_current(Adc *p_adc, const uint8_t uc_ibctl);
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void adc_enable_ts(Adc *p_adc);
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void adc_disable_ts(Adc *p_adc);
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#elif SAM3N_SERIES
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void adc_configure_timing(Adc *p_adc, const uint8_t uc_tracking);
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#elif SAM3U_SERIES
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void adc_configure_timing(Adc *p_adc, const uint32_t ul_sh);
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#endif
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#if SAM3SD8_SERIES || SAM4S_SERIES
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void adc_set_calibmode(Adc *p_adc);
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#endif
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#if SAM3U_SERIES
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uint32_t adc12b_init(Adc12b *p_adc, const uint32_t ul_mck, const uint32_t ul_adc_clock,
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const uint32_t ul_startuptime, const uint32_t ul_offmode_startuptime);
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void adc12b_set_resolution(Adc12b *p_adc, const enum adc_resolution_t resolution);
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void adc12b_configure_trigger(Adc12b *p_adc, const enum adc_trigger_t trigger);
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void adc12b_configure_power_save(Adc12b *p_adc, const uint8_t uc_sleep, const uint8_t uc_offmode);
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void adc12b_configure_timing(Adc12b *p_adc, const uint32_t ul_sh);
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void adc12b_start(Adc12b *p_adc);
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void adc12b_stop(Adc12b *p_adc);
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void adc12b_enable_channel(Adc12b *p_adc, const enum adc_channel_num_t adc_ch);
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void adc12b_disable_channel(Adc12b *p_adc, const enum adc_channel_num_t adc_ch);
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void adc12b_enable_all_channel(Adc12b *p_adc);
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void adc12b_disable_all_channel(Adc12b *p_adc);
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uint32_t adc12b_get_channel_status(const Adc12b *p_adc,const enum adc_channel_num_t adc_ch);
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uint32_t adc12b_get_channel_value(const Adc12b *p_adc, const enum adc_channel_num_t adc_ch);
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uint32_t adc12b_get_latest_value(const Adc12b *p_adc);
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void adc12b_enable_differential_input(Adc12b *p_adc);
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void adc12b_disable_differential_input(Adc12b *p_adc);
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void adc12b_enable_input_offset(Adc12b *p_adc);
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void adc12b_disable_input_offset(Adc12b *p_adc);
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void adc12b_set_input_gain(Adc12b *p_adc, const enum adc_gainvalue_t uc_gain);
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uint32_t adc12b_get_actual_adc_clock(const Adc12b *p_adc, const uint32_t ul_mck);
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void adc12b_enable_interrupt(Adc12b *p_adc, const uint32_t ul_source);
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void adc12b_disable_interrupt(Adc12b *p_adc, const uint32_t ul_source);
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uint32_t adc12b_get_interrupt_mask(const Adc12b *p_adc);
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uint32_t adc12b_get_status(const Adc12b *p_adc);
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void adc12b_set_bias_current(Adc12b *p_adc, const uint8_t uc_ibctl);
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Pdc *adc12b_get_pdc_base(const Adc12b *p_adc);
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#endif
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/// @endcond
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#endif /* ADC_H_INCLUDED */
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