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68 lines
5.2 KiB
C
68 lines
5.2 KiB
C
/* $asf_license$ */
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#ifndef _SAM3S8_SSC_INSTANCE_
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#define _SAM3S8_SSC_INSTANCE_
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/* ========== Register definition for SSC peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */
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#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */
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#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
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#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
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#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
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#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
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#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */
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#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
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#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
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#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
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#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
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#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
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#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */
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#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
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#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
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#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
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#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
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#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
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#define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
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#define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */
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#define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
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#define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
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#define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
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#define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
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#define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
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#define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
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#define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */
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#define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */
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#else
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#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
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#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
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#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
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#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
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#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
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#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
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#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
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#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
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#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
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#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
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#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
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#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
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#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
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#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
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#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
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#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
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#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
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#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
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#define REG_SSC_RPR (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
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#define REG_SSC_RCR (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
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#define REG_SSC_TPR (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
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#define REG_SSC_TCR (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
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#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
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#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
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#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
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#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
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#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
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#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3S8_SSC_INSTANCE_ */
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