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271 lines
19 KiB
C
271 lines
19 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3U_DMAC_COMPONENT_
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#define _SAM3U_DMAC_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR DMA Controller */
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/* ============================================================================= */
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/** \addtogroup SAM3U_DMAC DMA Controller */
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/*@{*/
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#ifndef __ASSEMBLY__
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/** \brief DmacCh_num hardware registers */
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typedef struct {
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RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
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RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
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RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
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RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
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RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
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RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
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RwReg DMAC_SPIP; /**< \brief (DmacCh_num Offset: 0x18) DMAC Channel Source Picture in Picture Configuration Register */
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RwReg DMAC_DPIP; /**< \brief (DmacCh_num Offset: 0x1C) DMAC Channel Destination Picture in Picture Configuration Register */
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RoReg Reserved1[2];
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} DmacCh_num;
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/** \brief Dmac hardware registers */
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#define DMACCH_NUM_NUMBER 4
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typedef struct {
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RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
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RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
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RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
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RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
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RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
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RwReg DMAC_SYNC; /**< \brief (Dmac Offset: 0x014) DMAC Request Synchronization Register */
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WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
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WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
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RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
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RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
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WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
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WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
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RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
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RoReg Reserved1[2];
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DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
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} Dmac;
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#endif /* __ASSEMBLY__ */
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/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
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#define DMAC_GCFG_IF0_BIGEND (0x1u << 0) /**< \brief (DMAC_GCFG) */
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#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) */
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/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
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#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */
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/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
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#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) */
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#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) */
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/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
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#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) */
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#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) */
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/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
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#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) */
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#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) */
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/* -------- DMAC_SYNC : (DMAC Offset: 0x014) DMAC Request Synchronization Register -------- */
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#define DMAC_SYNC_SYR0 (0x1u << 0) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR1 (0x1u << 1) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR2 (0x1u << 2) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR3 (0x1u << 3) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR4 (0x1u << 4) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR5 (0x1u << 5) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR6 (0x1u << 6) /**< \brief (DMAC_SYNC) */
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#define DMAC_SYNC_SYR7 (0x1u << 7) /**< \brief (DMAC_SYNC) */
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/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */
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#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) */
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#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) */
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/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. -------- */
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#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) */
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#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) */
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/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. -------- */
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#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) */
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#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) */
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/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. -------- */
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#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) */
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#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) */
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/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
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#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) */
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#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) */
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/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
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#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) */
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#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) */
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/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
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#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) */
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#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) */
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/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
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#define DMAC_SADDR_SADDRx_Pos 0
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#define DMAC_SADDR_SADDRx_Msk (0xffffffffu << DMAC_SADDR_SADDRx_Pos) /**< \brief (DMAC_SADDR) */
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#define DMAC_SADDR_SADDRx(value) ((DMAC_SADDR_SADDRx_Msk & ((value) << DMAC_SADDR_SADDRx_Pos)))
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/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
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#define DMAC_DADDR_DADDRx_Pos 0
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#define DMAC_DADDR_DADDRx_Msk (0xffffffffu << DMAC_DADDR_DADDRx_Pos) /**< \brief (DMAC_DADDR) */
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#define DMAC_DADDR_DADDRx(value) ((DMAC_DADDR_DADDRx_Msk & ((value) << DMAC_DADDR_DADDRx_Pos)))
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/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
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#define DMAC_DSCR_DSCRx_IF_Pos 0
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#define DMAC_DSCR_DSCRx_IF_Msk (0x3u << DMAC_DSCR_DSCRx_IF_Pos) /**< \brief (DMAC_DSCR) */
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#define DMAC_DSCR_DSCRx_IF(value) ((DMAC_DSCR_DSCRx_IF_Msk & ((value) << DMAC_DSCR_DSCRx_IF_Pos)))
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#define DMAC_DSCR_DSCRx_Pos 2
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#define DMAC_DSCR_DSCRx_Msk (0x3fffffffu << DMAC_DSCR_DSCRx_Pos) /**< \brief (DMAC_DSCR) */
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#define DMAC_DSCR_DSCRx(value) ((DMAC_DSCR_DSCRx_Msk & ((value) << DMAC_DSCR_DSCRx_Pos)))
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/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
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#define DMAC_CTRLA_BTSIZE_Pos 0
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#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) */
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#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
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#define DMAC_CTRLA_SCSIZE_Pos 16
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#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) */
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#define DMAC_CTRLA_SCSIZE(value) ((DMAC_CTRLA_SCSIZE_Msk & ((value) << DMAC_CTRLA_SCSIZE_Pos)))
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#define DMAC_CTRLA_DCSIZE_Pos 20
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#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) */
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#define DMAC_CTRLA_DCSIZE(value) ((DMAC_CTRLA_DCSIZE_Msk & ((value) << DMAC_CTRLA_DCSIZE_Pos)))
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#define DMAC_CTRLA_SRC_WIDTH_Pos 24
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#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) */
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#define DMAC_CTRLA_SRC_WIDTH(value) ((DMAC_CTRLA_SRC_WIDTH_Msk & ((value) << DMAC_CTRLA_SRC_WIDTH_Pos)))
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#define DMAC_CTRLA_DST_WIDTH_Pos 28
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#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) */
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#define DMAC_CTRLA_DST_WIDTH(value) ((DMAC_CTRLA_DST_WIDTH_Msk & ((value) << DMAC_CTRLA_DST_WIDTH_Pos)))
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#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */
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/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
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#define DMAC_CTRLB_SIF_Pos 0
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#define DMAC_CTRLB_SIF_Msk (0x3u << DMAC_CTRLB_SIF_Pos) /**< \brief (DMAC_CTRLB) Source Interface Selection Field */
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#define DMAC_CTRLB_SIF(value) ((DMAC_CTRLB_SIF_Msk & ((value) << DMAC_CTRLB_SIF_Pos)))
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#define DMAC_CTRLB_DIF_Pos 4
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#define DMAC_CTRLB_DIF_Msk (0x3u << DMAC_CTRLB_DIF_Pos) /**< \brief (DMAC_CTRLB) Destination Interface Selection Field */
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#define DMAC_CTRLB_DIF(value) ((DMAC_CTRLB_DIF_Msk & ((value) << DMAC_CTRLB_DIF_Pos)))
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#define DMAC_CTRLB_SRC_PIP (0x1u << 8) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_DST_PIP (0x1u << 12) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_FC_Pos 21
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#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_FC(value) ((DMAC_CTRLB_FC_Msk & ((value) << DMAC_CTRLB_FC_Pos)))
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#define DMAC_CTRLB_SRC_INCR_Pos 24
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#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_SRC_INCR(value) ((DMAC_CTRLB_SRC_INCR_Msk & ((value) << DMAC_CTRLB_SRC_INCR_Pos)))
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#define DMAC_CTRLB_DST_INCR_Pos 28
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#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_DST_INCR(value) ((DMAC_CTRLB_DST_INCR_Msk & ((value) << DMAC_CTRLB_DST_INCR_Pos)))
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#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */
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#define DMAC_CTRLB_AUTO (0x1u << 31) /**< \brief (DMAC_CTRLB) */
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/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
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#define DMAC_CFG_SRC_PER_Pos 0
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#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
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#define DMAC_CFG_DST_PER_Pos 4
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#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
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#define DMAC_CFG_SRC_REP (0x1u << 8) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_DST_REP (0x1u << 12) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_AHB_PROT_Pos 24
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#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
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#define DMAC_CFG_FIFOCFG_Pos 28
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#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) */
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#define DMAC_CFG_FIFOCFG(value) ((DMAC_CFG_FIFOCFG_Msk & ((value) << DMAC_CFG_FIFOCFG_Pos)))
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/* -------- DMAC_SPIP : (DMAC Offset: N/A) DMAC Channel Source Picture in Picture Configuration Register -------- */
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#define DMAC_SPIP_SPIP_HOLE_Pos 0
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#define DMAC_SPIP_SPIP_HOLE_Msk (0xffffu << DMAC_SPIP_SPIP_HOLE_Pos) /**< \brief (DMAC_SPIP) */
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#define DMAC_SPIP_SPIP_HOLE(value) ((DMAC_SPIP_SPIP_HOLE_Msk & ((value) << DMAC_SPIP_SPIP_HOLE_Pos)))
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#define DMAC_SPIP_SPIP_BOUNDARY_Pos 16
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#define DMAC_SPIP_SPIP_BOUNDARY_Msk (0x3ffu << DMAC_SPIP_SPIP_BOUNDARY_Pos) /**< \brief (DMAC_SPIP) */
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#define DMAC_SPIP_SPIP_BOUNDARY(value) ((DMAC_SPIP_SPIP_BOUNDARY_Msk & ((value) << DMAC_SPIP_SPIP_BOUNDARY_Pos)))
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/* -------- DMAC_DPIP : (DMAC Offset: N/A) DMAC Channel Destination Picture in Picture Configuration Register -------- */
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#define DMAC_DPIP_DPIP_HOLE_Pos 0
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#define DMAC_DPIP_DPIP_HOLE_Msk (0xffffu << DMAC_DPIP_DPIP_HOLE_Pos) /**< \brief (DMAC_DPIP) */
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#define DMAC_DPIP_DPIP_HOLE(value) ((DMAC_DPIP_DPIP_HOLE_Msk & ((value) << DMAC_DPIP_DPIP_HOLE_Pos)))
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#define DMAC_DPIP_DPIP_BOUNDARY_Pos 16
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#define DMAC_DPIP_DPIP_BOUNDARY_Msk (0x3ffu << DMAC_DPIP_DPIP_BOUNDARY_Pos) /**< \brief (DMAC_DPIP) */
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#define DMAC_DPIP_DPIP_BOUNDARY(value) ((DMAC_DPIP_DPIP_BOUNDARY_Msk & ((value) << DMAC_DPIP_DPIP_BOUNDARY_Pos)))
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/*@}*/
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#endif /* _SAM3U_DMAC_COMPONENT_ */
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