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50 lines
2.6 KiB
C
50 lines
2.6 KiB
C
/* $asf_license$ */
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#ifndef _SAM3XA_EFC_COMPONENT_
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#define _SAM3XA_EFC_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
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/* ============================================================================= */
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/** \addtogroup SAM3XA_EFC Embedded Flash Controller */
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/*@{*/
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#ifndef __ASSEMBLY__
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/** \brief Efc hardware registers */
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typedef struct {
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RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
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WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
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RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
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RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
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} Efc;
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#endif /* __ASSEMBLY__ */
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/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
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#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
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#define EEFC_FMR_FWS_Pos 8
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#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
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#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
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#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
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#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
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/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
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#define EEFC_FCR_FCMD_Pos 0
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#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
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#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
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#define EEFC_FCR_FARG_Pos 8
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#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
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#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
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#define EEFC_FCR_FKEY_Pos 24
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#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
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#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
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/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
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#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
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#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
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#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
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/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
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#define EEFC_FRR_FVALUE_Pos 0
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#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
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/*@}*/
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#endif /* _SAM3XA_EFC_COMPONENT_ */
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