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38 lines
2.5 KiB
C
38 lines
2.5 KiB
C
/* $asf_license$ */
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#ifndef _SAM3XA_RTC_INSTANCE_
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#define _SAM3XA_RTC_INSTANCE_
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/* ========== Register definition for RTC peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_RTC_CR (0x400E1A60U) /**< \brief (RTC) Control Register */
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#define REG_RTC_MR (0x400E1A64U) /**< \brief (RTC) Mode Register */
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#define REG_RTC_TIMR (0x400E1A68U) /**< \brief (RTC) Time Register */
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#define REG_RTC_CALR (0x400E1A6CU) /**< \brief (RTC) Calendar Register */
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#define REG_RTC_TIMALR (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
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#define REG_RTC_CALALR (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
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#define REG_RTC_SR (0x400E1A78U) /**< \brief (RTC) Status Register */
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#define REG_RTC_SCCR (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
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#define REG_RTC_IER (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
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#define REG_RTC_VER (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
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#define REG_RTC_WPMR (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
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#else
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#define REG_RTC_CR (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */
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#define REG_RTC_MR (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */
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#define REG_RTC_TIMR (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */
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#define REG_RTC_CALR (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */
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#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
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#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
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#define REG_RTC_SR (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */
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#define REG_RTC_SCCR (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
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#define REG_RTC_IER (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
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#define REG_RTC_VER (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
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#define REG_RTC_WPMR (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3XA_RTC_INSTANCE_ */
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