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70 lines
5.7 KiB
C
70 lines
5.7 KiB
C
/* $asf_license$ */
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#ifndef _SAM3XA_USART1_INSTANCE_
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#define _SAM3XA_USART1_INSTANCE_
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/* ========== Register definition for USART1 peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_USART1_CR (0x4009C000U) /**< \brief (USART1) Control Register */
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#define REG_USART1_MR (0x4009C004U) /**< \brief (USART1) Mode Register */
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#define REG_USART1_IER (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
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#define REG_USART1_IDR (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
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#define REG_USART1_IMR (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
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#define REG_USART1_CSR (0x4009C014U) /**< \brief (USART1) Channel Status Register */
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#define REG_USART1_RHR (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
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#define REG_USART1_THR (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
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#define REG_USART1_BRGR (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
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#define REG_USART1_RTOR (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
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#define REG_USART1_TTGR (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
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#define REG_USART1_FIDI (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
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#define REG_USART1_NER (0x4009C044U) /**< \brief (USART1) Number of Errors Register */
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#define REG_USART1_IF (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
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#define REG_USART1_MAN (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
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#define REG_USART1_LINMR (0x4009C054U) /**< \brief (USART1) LIN Mode Register */
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#define REG_USART1_LINIR (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
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#define REG_USART1_WPMR (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
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#define REG_USART1_WPSR (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
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#define REG_USART1_RPR (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
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#define REG_USART1_RCR (0x4009C104U) /**< \brief (USART1) Receive Counter Register */
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#define REG_USART1_TPR (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
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#define REG_USART1_TCR (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
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#define REG_USART1_RNPR (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
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#define REG_USART1_RNCR (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
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#define REG_USART1_TNPR (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
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#define REG_USART1_TNCR (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
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#define REG_USART1_PTCR (0x4009C120U) /**< \brief (USART1) Transfer Control Register */
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#define REG_USART1_PTSR (0x4009C124U) /**< \brief (USART1) Transfer Status Register */
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#else
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#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */
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#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */
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#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
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#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
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#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
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#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */
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#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
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#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
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#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
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#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
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#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
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#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
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#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */
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#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
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#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
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#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */
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#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
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#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
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#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
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#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
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#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */
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#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
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#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
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#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
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#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
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#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
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#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
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#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */
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#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3XA_USART1_INSTANCE_ */
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