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30 lines
2.2 KiB
C
30 lines
2.2 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3U_ADC_INSTANCE_
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#define _SAM3U_ADC_INSTANCE_
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/* ========== Register definition for ADC peripheral ========== */
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#define REG_ADC_CR REG_ACCESS(WoReg, 0x400AC000U) /**< \brief (ADC) Control Register */
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#define REG_ADC_MR REG_ACCESS(RwReg, 0x400AC004U) /**< \brief (ADC) Mode Register */
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#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400AC010U) /**< \brief (ADC) Channel Enable Register */
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#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (ADC) Channel Disable Register */
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#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400AC018U) /**< \brief (ADC) Channel Status Register */
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#define REG_ADC_SR REG_ACCESS(RoReg, 0x400AC01CU) /**< \brief (ADC) Status Register */
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#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
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#define REG_ADC_IER REG_ACCESS(WoReg, 0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
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#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
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#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
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#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400AC030U) /**< \brief (ADC) Channel Data Register */
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#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
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#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400AC104U) /**< \brief (ADC) Receive Counter Register */
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#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
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#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
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#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
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#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
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#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
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#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
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#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400AC120U) /**< \brief (ADC) Transfer Control Register */
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#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400AC124U) /**< \brief (ADC) Transfer Status Register */
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#endif /* _SAM3U_ADC_INSTANCE_ */
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