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50 lines
3.7 KiB
C
50 lines
3.7 KiB
C
/* $asf_license$ */
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#ifndef _SAM3S8_UART1_INSTANCE_
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#define _SAM3S8_UART1_INSTANCE_
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/* ========== Register definition for UART1 peripheral ========== */
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#ifdef __ASSEMBLY__
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#define REG_UART1_CR (0x400E0800U) /**< \brief (UART1) Control Register */
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#define REG_UART1_MR (0x400E0804U) /**< \brief (UART1) Mode Register */
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#define REG_UART1_IER (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
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#define REG_UART1_IDR (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
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#define REG_UART1_IMR (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
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#define REG_UART1_SR (0x400E0814U) /**< \brief (UART1) Status Register */
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#define REG_UART1_RHR (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
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#define REG_UART1_THR (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
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#define REG_UART1_BRGR (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
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#define REG_UART1_RPR (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
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#define REG_UART1_RCR (0x400E0904U) /**< \brief (UART1) Receive Counter Register */
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#define REG_UART1_TPR (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
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#define REG_UART1_TCR (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
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#define REG_UART1_RNPR (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
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#define REG_UART1_RNCR (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
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#define REG_UART1_TNPR (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
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#define REG_UART1_TNCR (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
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#define REG_UART1_PTCR (0x400E0920U) /**< \brief (UART1) Transfer Control Register */
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#define REG_UART1_PTSR (0x400E0924U) /**< \brief (UART1) Transfer Status Register */
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#else
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#define REG_UART1_CR (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
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#define REG_UART1_MR (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
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#define REG_UART1_IER (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
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#define REG_UART1_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
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#define REG_UART1_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
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#define REG_UART1_SR (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
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#define REG_UART1_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
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#define REG_UART1_THR (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
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#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
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#define REG_UART1_RPR (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
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#define REG_UART1_RCR (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */
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#define REG_UART1_TPR (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
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#define REG_UART1_TCR (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
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#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
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#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
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#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
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#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
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#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */
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#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */
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#endif /* __ASSEMBLY__ */
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#endif /* _SAM3S8_UART1_INSTANCE_ */
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