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152 lines
5.4 KiB
C
152 lines
5.4 KiB
C
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/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_MPU6050 MPU6050 Functions
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* @brief Deals with the hardware interface to the 3-axis gyro
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* @{
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*
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* @file pios_MPU6050.h
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* @author David "Buzz" Carlson (buzz@chebuzz.com)
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* The OpenPilot Team, http://www.openpilot.org Copyright (C) 2011.
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* @brief MPU6050 3-axis gyor function headers
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* @see The GNU Public License (GPL) Version 3
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*
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******************************************************************************
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef PIOS_MPU6050_H
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#define PIOS_MPU6050_H
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#include "pios.h"
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/* MPU6050 Addresses */
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#define PIOS_MPU6050_I2C_ADDR 0x69
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#define PIOS_MPU6050_X_MSB_OFFSET_REG 0x43
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#define PIOS_MPU6050_X_LSB_OFFSET_REG 0x44
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#define PIOS_MPU6050_Y_MSB_OFFSET_REG 0x45
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#define PIOS_MPU6050_Y_LSB_OFFSET_REG 0x46
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#define PIOS_MPU6050_Z_MSB_OFFSET_REG 0x47
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#define PIOS_MPU6050_Z_LSB_OFFSET_REG 0x48
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#define PIOS_MPU6050_FIFO_EN_REG 0x23
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#define PIOS_MPU6050_SMPLRT_DIV_REG 0X19
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#define PIOS_MPU6050_DLPF_CFG_REG 0X16
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#define PIOS_MPU6050_INT_CFG_REG 0x37
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#define PIOS_MPU6050_INT_STATUS_REG 0x3A
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#define PIOS_MPU6050_TEMP_OUT_MSB 0x41
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#define PIOS_MPU6050_TEMP_OUT_LSB 0x42
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#define PIOS_MPU6050_GYRO_X_OUT_MSB 0x1D
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#define PIOS_MPU6050_GYRO_X_OUT_LSB 0x1E
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#define PIOS_MPU6050_GYRO_Y_OUT_MSB 0x1F
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#define PIOS_MPU6050_GYRO_Y_OUT_LSB 0x20
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#define PIOS_MPU6050_GYRO_Z_OUT_MSB 0x21
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#define PIOS_MPU6050_GYRO_Z_OUT_LSB 0x22
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#define PIOS_MPU6050_FIFO_CNT_MSB 0x72
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#define PIOS_MPU6050_FIFO_CNT_LSB 0x73
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#define PIOS_MPU6050_FIFO_REG 0x74
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#define PIOS_MPU6050_USER_CTRL_REG 0x6A
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#define PIOS_MPU6050_PWR_MGMT_REG 0x6C
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#define PIOS_MPU6050_WHOAMI 0x75
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/* FIFO enable for storing different values */
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#define PIOS_MPU6050_FIFO_TEMP_OUT 0x80
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#define PIOS_MPU6050_FIFO_GYRO_X_OUT 0x40
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#define PIOS_MPU6050_FIFO_GYRO_Y_OUT 0x20
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#define PIOS_MPU6050_FIFO_GYRO_Z_OUT 0x10
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#define PIOS_MPU6050_FIFO_FOOTER 0x01
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/* Interrupt Configuration */
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#define PIOS_MPU6050_INT_ACTL 0x80
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#define PIOS_MPU6050_INT_OPEN 0x40
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#define PIOS_MPU6050_INT_LATCH_EN 0x20
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#define PIOS_MPU6050_INT_CLR_ANYRD 0x10
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#define PIOS_MPU6050_INT_IMU_RDY 0x04
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#define PIOS_MPU6050_INT_DATA_RDY 0x01
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/* Interrupt status */
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#define PIOS_MPU6050_INT_STATUS_FIFO_FULL 0x80
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#define PIOS_MPU6050_INT_STATUS_IMU_RDY 0X04
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#define PIOS_MPU6050_INT_STATUS_DATA_RDY 0X01
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/* User control functionality */
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#define PIOS_MPU6050_USERCTL_FIFO_EN 0X40
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#define PIOS_MPU6050_USERCTL_FIFO_RST 0X02
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#define PIOS_MPU6050_USERCTL_GYRO_RST 0X01
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/* Power management and clock selection */
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#define PIOS_MPU6050_PWRMGMT_IMU_RST 0X80
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#define PIOS_MPU6050_PWRMGMT_INTERN_CLK 0X00
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#define PIOS_MPU6050_PWRMGMT_PLL_X_CLK 0X01
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#define PIOS_MPU6050_PWRMGMT_PLL_Y_CLK 0X02
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#define PIOS_MPU6050_PWRMGMT_PLL_Z_CLK 0X03
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#define PIOS_MPU6050_PWRMGMT_STOP_CLK 0X07
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enum pios_mpu6050_range {
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PIOS_MPU6050_SCALE_250_DEG = 0x00,
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PIOS_MPU6050_SCALE_500_DEG = 0x01,
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PIOS_MPU6050_SCALE_1000_DEG = 0x02,
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PIOS_MPU6050_SCALE_2000_DEG = 0x03
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};
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enum pios_mpu6050_filter {
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PIOS_MPU6050_LOWPASS_256_HZ = 0x00,
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PIOS_MPU6050_LOWPASS_188_HZ = 0x01,
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PIOS_MPU6050_LOWPASS_98_HZ = 0x02,
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PIOS_MPU6050_LOWPASS_42_HZ = 0x03,
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PIOS_MPU6050_LOWPASS_20_HZ = 0x04,
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PIOS_MPU6050_LOWPASS_10_HZ = 0x05,
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PIOS_MPU6050_LOWPASS_5_HZ = 0x06
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};
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struct pios_mpu6050_data {
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int16_t x;
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int16_t y;
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int16_t z;
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int16_t temperature;
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};
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struct pios_mpu6050_cfg {
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struct stm32_gpio drdy;
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struct stm32_exti eoc_exti;
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struct stm32_irq eoc_irq;
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uint8_t Fifo_store; /* FIFO storage of different readings (See datasheet page 31 for more details) */
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uint8_t Smpl_rate_div; /* Sample rate divider to use (See datasheet page 32 for more details) */
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uint8_t Interrupt_cfg; /* Interrupt configuration (See datasheet page 35 for more details) */
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uint8_t User_ctl; /* User control settings (See datasheet page 41 for more details) */
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uint8_t Pwr_mgmt_clk; /* Power management and clock selection (See datasheet page 32 for more details) */
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enum pios_mpu6050_range range;
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enum pios_mpu6050_filter filter;
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};
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/* Public Functions */
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extern void PIOS_MPU6050_Init(const struct pios_mpu6050_cfg * cfg);
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extern int32_t PIOS_MPU6050_ReadFifo(struct pios_mpu6050_data * buffer);
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extern int32_t PIOS_MPU6050_ReadGyros(struct pios_mpu6050_data * buffer);
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extern int32_t PIOS_MPU6050_ReadID();
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extern uint8_t PIOS_MPU6050_Test();
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extern float PIOS_MPU6050_GetScale();
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#endif /* PIOS_MPU6050_H */
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/**
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* @}
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* @}
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*/
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